Boost-Free Cryogenic Gain-Cell Memory for Data Retention
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Solution Overview
Problem
Existing cryogenic energy-efficient memory systems face challenges in achieving longer data retention time, efficient dual-port read operations, and reducing high power consumption, especially in high-density and high-capacity applications.
Innovation Solution
A cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) memory design with a universal and different address decoder, bitline segmentation, and wordline voltage off-chip tuning to support dual-port read operations and optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wordline voltage boosting scheme is used to ensure good data writing in conventional eDRAM, then data retention is improved, but threshold voltage increases as temperature decreases making the scheme less effective at cryogenic temperature and affecting device lifespan
Solution Approach 1:
The patent changes the operating parameters by using fixed wordline voltage without boosting, relying instead on the inherent low leakage characteristics of CMOS transistors at cryogenic temperatures to maintain data retention. This parameter change eliminates the need for high voltage boosting that becomes ineffective at low temperatures.
Solution Approach 2:
The patent converts the harmful effect of increased threshold voltage at cryogenic temperatures into a beneficial effect by utilizing the low leakage current characteristic that naturally occurs at these temperatures. The low leakage current, which would normally be considered a limitation, is instead exploited to achieve long data retention times without requiring voltage boosting.
2Loss of energy
If two unrelated access ports are used to separate read and write operations, then data leakage of memory node is reduced, but high-performance dual-port read operation cannot be achieved and data bandwidth requirement cannot be met
Solution Approach 1:
The patent merges the read and write access ports into a unified dual-port structure where both ports share common resources including the memory cell array and sense amplifiers. This merging enables simultaneous read and write operations as well as dual-port read operations, significantly increasing data bandwidth while maintaining low data leakage through proper port control.
Solution Approach 2:
The access ports are designed with multi-functionality, capable of performing read operations, write operations, and dual-port read operations. The ports can be configured to access different memory cells simultaneously or sequentially, providing flexible operation modes that meet various data bandwidth requirements while maintaining data integrity.
3Productivity
If high-power operation of the circuit is used for frequent read and write operations in high-density and high-capacity memory, then operational performance is improved, but cooling cost of cryogenic system increases greatly
Solution Approach 1:
The patent changes the power consumption parameters by optimizing the memory cell design and access mechanisms to reduce the power required for read and write operations. By using efficient transistor-level operations and minimizing unnecessary voltage boosting, the circuit achieves good operational performance with significantly reduced power consumption, thereby lowering cooling costs.
Solution Approach 2:
The memory system leverages the natural low-temperature environment of the cryogenic system to reduce leakage current and minimize power consumption. The system self-adapts to the cold environment, utilizing the inherent properties of semiconductor devices at low temperatures to achieve efficient operation without requiring additional cooling power.
Data Source
AI summary
An energy-efficient memory for cryogenic computing is provided. The energy-efficient memory includes a plurality of memory banks, where each of the memory banks includes a cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) macro module, a universal address decoder, and a different address decoder. The CSDB-GC macro module includes a plurality of columns of local blocks, and each of the local blocks includes a plurality of CSDB-GC memory cells. A final measurement result of a 16 Kb CSDB-eDRAM shows that the 16 Kb CSDB-eDRAM achieves data retention time (DRT) of 16.67 seconds, which is 2.6 times longer than DRT of a state-of-the-art cryogenic eDRAM at a temperature of 4.2 K, and achieves lower refresh power (0.11 pW/Kb). In addition, the 16 Kb CSDB-eDRAM also achieves shorter access time, namely, 710 ps (1.41 GHz). Compared with the state-of-the-art work, the 16 Kb CSDB-eDRAM has a lowest dynamic power consumption overhead, namely, 49.23 uW/Kb.