Boost Logic Buffering for Memory Sensing Window

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Solution Overview

Problem

Existing memory access technologies face challenges in maintaining a sufficient sensing window, especially when reading multi-level memory cells, due to the dependence of boost voltage on memory cell state, which can lead to slower read operations and increased wait times.

Innovation Solution

The implementation of boost logic that generates, maintains, and adjusts a boost voltage, including a boost source and interfaces that buffer the load, allowing the boost voltage to be independent of the memory cell state, thereby preventing voltage drops and enabling faster read operations across both single and multi-level memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If boost voltage is generated without buffering, then the sensing window can be increased, but the boost voltage becomes dependent on memory cell state causing voltage drops and slower read operations

Engineering Contradiction:
Improveread operation timeVSAvoidboost voltage stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

A buffer circuit is introduced as an intermediary between the boost voltage generation circuit and the memory cell array. This buffer isolates the boost voltage from direct dependence on memory cell state, preventing voltage drops while maintaining the enhanced sensing window. The buffer acts as a mediator that decouples the relationship between memory cell access and boost voltage stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If boost voltage is generated for each sense amplifier, then the sensing window is increased, but the device complexity increases due to multiple boost sources

Engineering Contradiction:
Improvesensing timeVSAvoidboost logic structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

Multiple sense amplifiers share a common boost voltage generation circuit rather than each having its own independent boost source. The single boosted node serves multiple sense amplifiers simultaneously, reducing the overall number of boost circuits required while still providing the sensing window enhancement to all amplifiers. This consolidation reduces device complexity and component count.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If wait time is reduced for faster memory access, then productivity increases, but the sensing window becomes insufficient for reliable multi-level memory cell reading

Engineering Contradiction:
Improvememory access speedVSAvoidsensing window adequacy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The boost voltage is generated and applied to the sense amplifier inputs before the actual sensing operation begins. This preliminary application of boosted voltage ensures that when the sensing window opens, the amplifiers are already in an optimized state for rapid detection. The boost is prepared in advance, allowing the sensing operation to proceed quickly without sacrificing detection precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9312018B1Sensing with boost
Publication Date: 2016.04.12 INTEL NDTM US LLC
  • US9312018B1 patent drawing
  • US9312018B1 patent drawing
  • US9312018B1 patent drawing

AI summary

The present disclosure relates to sensing with boost. An apparatus includes boost logic. Boost logic includes a boost source and a plurality of boost interfaces coupled to the boost source. The boost source is configured to provide a boost clamp voltage to each of the plurality of boost interfaces. Each of the plurality of boost interfaces includes a respective buffer configured to buffer the boost source from a respective load. Each boost interface is configured to provide a boost voltage to the respective load. The boost voltage configured to increase a sense window. The boost voltage related to the boost clamp voltage.