Boost PFC Controller Cold Start Overvoltage Protection

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Solution Overview

Problem

Boost PFC converters face challenges in distinguishing between genuine overvoltage conditions and transient high voltage conditions during initial operation, leading to potential damage due to high voltages across thermistors, as existing systems lack the capability to accurately differentiate between these states and take appropriate preventive measures.

Innovation Solution

A boost PFC converter system with a PFC controller that determines whether the current through the inductor reaches zero within a predetermined time after the voltage drops below a threshold, outputting signals to differentiate between overvoltage and cold start conditions, thereby taking mitigating actions such as reducing the switching duty cycle or turning off the converter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the PFC converter operates during initial cold start conditions, then the converter can start up and begin operation, but high voltages across the thermistor may cause potential damage

Engineering Contradiction:
Improveconverter startup capabilityVSAvoidhigh voltage damage risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary detection of inductor current status before allowing full operation. The zero current detector and timer circuit proactively identify whether the inductor current has reached zero within the expected time frame, preventing damage before it occurs by anticipating the cold start condition and triggering appropriate protective measures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors the inductor current through the zero current detector and compares it against expected timing parameters. This feedback mechanism allows the controller to distinguish between genuine overvoltage conditions and transient cold start conditions, enabling selective activation of protection circuits only when necessary

Inventive Principle:
Principle #23Feedback

2Reliability

If the system implements comprehensive overvoltage protection, then damage from genuine overvoltage conditions is prevented, but false detection may cause unnecessary shutdowns or inefficiencies

Engineering Contradiction:
Improveovervoltage protection accuracyVSAvoidconverter operational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The protection system dynamically adjusts its response based on real-time detection of inductor current behavior. Rather than using a static protection threshold, the system evaluates whether the current reaches zero within a predetermined time window, allowing adaptive differentiation between transient cold start conditions and genuine overvoltage faults, thereby avoiding unnecessary shutdowns

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The protection mechanism is segmented into distinct detection and response stages. The zero current detector separately monitors current status, the timer independently evaluates timing parameters, and the controller integrates these separate signals to make protection decisions. This segmentation allows precise identification of cold start conditions without triggering false overvoltage protection

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11671006B2Power factor correction boost converter having an on-time responsive to negative current
Publication Date: 2023.06.06 TEXAS INSTRUMENTS INC
  • US11671006B2 patent drawing
  • US11671006B2 patent drawing
  • US11671006B2 patent drawing

AI summary

In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.