Integrated Boost-SEPIC Converter for Dual Low-Voltage Outputs
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Solution Overview
Problem
Existing emergency LED drivers face inefficiencies and supply chain issues due to the use of cascaded boost and synchronous buck topologies, which are lossy, costly, and require additional controllers or switching regulator chips.
Innovation Solution
An integrated boost-sepic converter design that includes a first inductance, capacitance, and diodes, regulated by a voltage control element, providing both regulated and boosted outputs without relying on discrete switching regulator chips, and incorporates a battery charger and control circuit for efficient power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If cascaded boost and synchronous buck topologies are used, then regulated voltage and boosted voltage can be generated from battery voltage, but conversion efficiency deteriorates and additional controllers and gate drives are required
Solution Approach 1:
The patent merges the boost converter and synchronous buck converter into a single integrated circuit chip, combining multiple voltage regulation functions (boost, buck, and LDO) into one device. This integration eliminates the need for separate controllers and gate drives, reducing component count while maintaining the ability to generate both regulated and boosted voltages from the battery input
Solution Approach 2:
The integrated chip provides multiple operating modes and voltage regulation topologies (boost converter, synchronous buck converter, and LDO regulator) within a single device, enabling it to perform multiple functions: generating regulated voltage, generating boosted voltage, and charging the battery from mains supply, all through one universal component
2Loss of energy
If synchronous buck is used, then higher efficiency is achieved, but additional controllers and gate drives are required which increases device complexity and cost
Solution Approach 1:
The patent integrates the synchronous buck converter controller, gate drives, and power switching elements into a single chip, eliminating the need for external controllers and gate drive circuits. The integrated design maintains high conversion efficiency while reducing the number of external components and simplifying the overall system architecture
Solution Approach 2:
The integrated chip contains self-contained control logic and gate drive circuits that automatically manage the synchronous buck converter operation. The device performs self-regulation and self-control functions internally, eliminating the need for external control circuits and reducing system complexity
3Loss of energy
If switching regulator chip is used, then efficiency is improved, but supply chain issues arise due to not being discrete and readily available
Solution Approach 1:
The patent combines multiple discrete components (boost converter, synchronous buck converter, LDO regulator, and battery charger) into a single integrated chip, creating a universal power management solution that is readily available and simplifies manufacturing by reducing the bill of materials to one primary component rather than multiple discrete devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated boost-sepic design achieves efficient power conversion matching cascaded boost and synchronous buck efficiency, is cost-effective, and avoids supply chain issues by using discrete components, offering robust and economic benefits across various topologies.
Implementation Method 1
a first inductance L1 and a voltage control element S1, arranged serially between an input potential Vin and a ground potential of the converter. The converter further comprises a first capacitance C1 and a second inductance L2, arranged serially in parallel to the voltage control element S1
Implementation Method 2
a first capacitance C1 and a second inductance L2, arranged serially in parallel to the voltage control element S1. The converter further comprises a second capacitance C2, arranged in parallel to the first capacitance C1
Implementation Method 3
The converter further comprises a first diode D0, arranged between a first low-voltage output potential Vout,µC of the converter and a common potential of the first capacitance C1 and the second inductance L2
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Disclosed is an integrated boost-sepic converter (1A, 1B). The converter (1A, 1B) comprises a first inductance (101, L1) and a voltage control element (102), arranged serially between an input potential (Vin) and a ground potential of the converter (1A, 1B). The converter (1A, 1B) further comprises a first capacitance (103, C1) and a second inductance (104, L2), arranged serially in parallel to the voltage control element (102). The converter (1A, 1B) further comprises a first diode (105, D0), arranged between a first low-voltage output potential (Vout,µC of the converter (1A, 1B) and a common potential of the first capacitance (103, C1) and the second inductance (104, L2). The converter (1A, 1B) further comprises a second diode (108, Dint), arranged between a second low-voltage output potential (Vout,GD) of the converter (1A, 1B) and a common potential of the first inductance (101, L1) and the voltage control element (102, S1). The converter (1A, 1B) is configured to regulate the first low-voltage output potential (Vout,µC) of the converter (1A, 1B) in dependence of the input potential (Vin) of the converter (1A, 1B); and to provide the second low-voltage output potential (Vout,GD = Vin + Vout,µC) of the converter (1A, 1B) as a sum of the input potential (Vin) and the first low-voltage output potential (Vout,µC). This avoids a cascaded LVPS design.