Boost Structures for NAND Flash Memory Programming
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in optimizing programming operations due to the need for high voltages, which can lead to program disturb and inefficiencies in verify and read operations, particularly in NAND flash memory devices.
Innovation Solution
The implementation of boost structures along NAND strings, which receive a boost voltage and are discharged to specific levels based on programming or verify states, allowing for lower programming voltages and concurrent characterization of multiple storage elements with a common word line voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high programming voltages are applied to NAND flash memory devices, then programming operations can be performed, but program disturb occurs and verify/read operations become inefficient
Solution Approach 1:
The memory array is divided into multiple blocks, each with independent boost structures. This segmentation allows selective boosting of only those blocks requiring programming operations, preventing program disturb in unselected blocks while maintaining efficient programming in selected blocks.
Solution Approach 2:
Boost structures are introduced as intermediary elements between the bit lines and the memory cells. These boost structures receive boosted voltages through bit lines and transfer them to selected memory cells, enabling high-voltage programming without applying high voltages to the entire memory array, thus preventing program disturb.
2Productivity
If high programming voltages are used, then programming can be performed, but verify and read operations become less efficient
Solution Approach 1:
The boost structures dynamically adjust their voltage levels based on operational requirements. During programming, they provide high boosted voltages; during verify and read operations, they operate at lower voltages. This dynamic voltage adjustment optimizes both programming capability and verify/read efficiency.
Solution Approach 2:
The voltage parameters of the boost structures are changed according to the operation type. Boosted voltages are applied during programming to enable efficient programming operations, while standard voltages are used during verify and read operations to improve their efficiency. This parameter change resolves the contradiction between programming capability and verify/read efficiency.
3Object-affected harmful factors
If boost structures are added to NAND strings, then programming voltages can be reduced, but device complexity increases
Solution Approach 1:
The boost structures serve multiple functions: they provide voltage boosting during programming, act as selection mechanisms for targeted programming, and enable reduced programming voltages. This multi-functionality justifies the added structural complexity by delivering multiple benefits from a single added component.
Solution Approach 2:
The boost structures are discharged to ground after each programming operation, recovering the voltage potential and preparing them for the next operation. This discharge mechanism allows the boost structures to be reused efficiently, amortizing the complexity overhead across multiple operations.
4Ease of operation
If conventional programming methods are used, then simple operations are performed, but multiple verify steps are required for multi-state memory
Solution Approach 1:
The boost structures are pre-charged to specific voltage levels corresponding to the desired programming state before the actual programming operation. This preliminary action allows the memory cells to be programmed directly to the target state in fewer steps, reducing the number of verify operations required for multi-state memory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for high programming voltages, minimizes program disturb, and enables efficient concurrent verification and reading of multiple storage elements, improving overall memory operation and reducing errors.
Implementation Method 1
a boost structure extends along the NAND string... applying the boost voltage to the NAND string such that the boost voltage is coupled to the boost structure via a location at which the boost structure communicates with the substrate
Implementation Method 2
The boost structure is discharged, at least in part, to a level which is based on a programming state to which a storage element is to be programmed
Data Source
AI summary
A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.