Boosted Bit Line Driver for NAND SSL Switching Margin
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Solution Overview
Problem
In low voltage integrated circuits, such as those used in NAND flash memory, the select string line (SSL) on/off margin for self-boosting operations is narrow due to smaller device areas and lower operation voltages, making it challenging to maintain effective switching control, especially in advanced CMOS technologies.
Innovation Solution
A device comprising a first power supply circuit and a second power supply circuit, along with a control circuit and a voltage driver, is used to generate and apply different voltage levels to a transistor, allowing for improved switching margins by boosting the control signal above the primary power supply voltage, enabling the transistor to be turned on or off effectively based on voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If lower operation voltages are used in advanced CMOS technology, then power consumption is reduced and device area is smaller, but the SSL on/off operating margin becomes narrower
Solution Approach 1:
The patent implements dynamic voltage control by separately controlling the bit line voltage (BL) and source line voltage (SSL) independently. The SSL voltage is dynamically adjusted to provide enhanced turn-off margin while the BL voltage is controlled for turn-on operations, allowing the system to adapt voltage levels based on operational requirements rather than using a fixed voltage level.
Solution Approach 2:
The patent changes the voltage parameter by introducing a higher voltage level (VDD2) from a second power supply circuit specifically for SSL operations. This parameter change allows the SSL to achieve sufficient voltage margin for reliable switching while the main circuit continues to operate at lower voltages (VDD1) for reduced power consumption.
2Area of stationary object
If smaller device area is used, then integration density increases, but the switching control margin for select gates deteriorates
Solution Approach 1:
The patent implements dynamic voltage control by separately controlling the bit line voltage (BL) and source line voltage (SSL) independently. The SSL voltage is dynamically adjusted to provide enhanced turn-off margin while the BL voltage is controlled for turn-on operations, allowing the system to adapt voltage levels based on operational requirements rather than using a fixed voltage level.
Solution Approach 2:
The patent changes the voltage parameter by introducing a higher voltage level (VDD2) from a second power supply circuit specifically for SSL operations. This parameter change allows the SSL to achieve sufficient voltage margin for reliable switching while the main circuit continues to operate at lower voltages (VDD1) for reduced power consumption.
3Reliability
If higher voltage levels are applied to improve switching margin, then SSL on/off control is enhanced, but power consumption increases
Solution Approach 1:
The patent segments the power supply into two separate circuits: a first power supply circuit (VDD1) for general low-voltage operations and a second power supply circuit (VDD2) for SSL-specific operations requiring higher voltage. This segmentation allows high voltage to be applied only where needed (SSL) and only during specific operations, rather than raising the voltage for the entire circuit.
Solution Approach 2:
The patent applies different voltage qualities to different parts of the circuit. The SSL receives higher voltage (VDD2) locally to ensure reliable switching, while the rest of the circuit operates at lower voltage (VDD1) to minimize power consumption. This local quality differentiation optimizes both reliability and power efficiency.
Data Source
AI summary
A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.