Boosted Bitlines for Storage Cell Verification in Memory Arrays
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Solution Overview
Problem
In NAND memory arrays, the precharge subinterval for bitline verification is prolonged due to capacitive coupling, leading to reduced performance and potential inaccuracies in programmed state sensing, as existing methods either reduce bitline verification voltage or shorten the subinterval, compromising either accuracy or peak currents.
Innovation Solution
Applying a non-zero offset voltage to non-target bitlines during the precharge subinterval allows for quicker ramp-up to the bitline verification voltage, maintaining high accuracy while shortening the precharge duration, thereby improving overall performance without impairing sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the precharge subinterval is prolonged to allow bitline voltage to settle, then the accuracy of programmed state sensing is improved, but the performance of the storage array deteriorates
Solution Approach 1:
The patent applies a non-zero offset voltage to non-target bitlines before the verify operation begins. This preliminary voltage application prepares the bitlines in advance, allowing them to settle more quickly when the verify operation starts, thus reducing the required precharge subinterval duration while maintaining sensing accuracy.
Solution Approach 2:
The patent changes the voltage parameter of non-target bitlines by applying a non-zero offset voltage during the precharge subinterval. This parameter change accelerates the voltage settling process on target bitlines, enabling a shorter precharge subinterval while maintaining the accuracy needed for programmed state sensing.
2Productivity
If the bitline verification voltage is reduced to shorten the precharge subinterval, then the performance is improved, but the sensing accuracy deteriorates
Solution Approach 1:
By applying a non-zero offset voltage to non-target bitlines in advance, the patent prepares the voltage conditions beforehand. This allows the system to use a shorter precharge subinterval without reducing the bitline verification voltage, thereby maintaining both performance and sensing accuracy.
3Productivity
If the precharge subinterval is shortened to improve performance, then the productivity is improved, but the bitline voltage settling accuracy deteriorates
Solution Approach 1:
The patent applies a non-zero offset voltage to non-target bitlines before the verify operation, preparing the voltage conditions in advance. This preliminary action ensures that when the shortened precharge subinterval begins, the bitlines can settle accurately within the reduced time frame, maintaining voltage settling accuracy while improving performance.
4Measurement precision
If the precharge subinterval is prolonged to ensure accurate sensing, then the measurement precision is improved, but the peak currents increase
Solution Approach 1:
By applying a non-zero offset voltage to non-target bitlines in advance, the patent reduces the voltage swing required during the verify operation. This preliminary preparation allows for a shorter precharge subinterval with reduced peak currents while maintaining accurate sensing.
Solution Approach 2:
The patent changes the voltage parameter of non-target bitlines by applying a non-zero offset, which reduces the voltage differential that needs to be settled during verification. This parameter change reduces the peak currents required while maintaining sensing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces bitline settling time and peak currents, enabling a shorter precharge subinterval without compromising the accuracy of programmed state sensing, thus enhancing the performance of the storage array.
Implementation Method 1
a voltage regulator to boost a supply voltage to the sense amplifier
Implementation Method 2
a sense amplifier having a transistor switch adapted to couple the voltage supply to the first bitline to ramp the voltage of the first bitline from the bitline verification voltage to the non-zero bitline offset voltage
Data Source
AI summary
In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.