Boosted Memory Controller Driver Circuitry for ISI Reduction
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Solution Overview
Problem
Conventional driver circuitries in memory controllers experience intersymbol interference (ISI) and voltage errors due to weak signal transitions and susceptibility to noise and crosstalk, especially at high frequencies, which degrade performance.
Innovation Solution
The driver circuitry includes main driver, hold driver, and boost circuitries, along with delay and boost slice circuitries, to mitigate ISI and voltage errors by controlling signal transitions and reducing rise time through AC coupling and delayed signal outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If NMOS transistors are used for pull up and pull down in low voltage application, then power consumption is reduced, but drive strength becomes weaker during pull up leading to increased rise time
Solution Approach 1:
The driver circuit is divided into multiple driver slices, each containing NMOS transistors for pull-up and pull-down operations. This segmentation allows independent control of each slice's drive strength while maintaining low power consumption, resolving the contradiction between power efficiency and drive capability.
Solution Approach 2:
The driver circuit implements dynamic control of drive strength by selectively activating different numbers of driver slices based on signal requirements. This dynamic adjustment allows the circuit to optimize between power consumption and rise time performance, achieving fast transitions when needed while conserving power during normal operation.
2Reliability
If data signals transition between positive and negative voltages, then signal integrity is maintained, but drive strength of NMOS transistor becomes weaker during pull up leading to increased rise time
Solution Approach 1:
Multiple driver slices are merged together to provide combined drive strength during voltage transitions. The parallel arrangement of NMOS transistors across slices accumulates their individual drive capabilities, maintaining fast rise times and signal integrity while preserving the low voltage operation benefits.
Solution Approach 2:
The driver circuit prepares for voltage transitions by pre-charging and pre-discharging nodes through controlled activation of driver slices. This preliminary action ensures that when full signal transitions occur, the rise time remains minimal and signal integrity is maintained throughout the transition process.
3Use of energy by moving object
If rise time of output voltage signal increases, then power consumption decreases, but susceptibility to supply noise and crosstalk increases resulting in intersymbol interference
Solution Approach 1:
The driver circuit dynamically adjusts its drive strength by controlling the number of active driver slices based on the required signal transition speed and noise environment. This dynamic control allows the system to achieve faster rise times when noise susceptibility is a concern while maintaining lower power consumption during stable signal conditions, effectively resolving the trade-off between power efficiency and noise immunity.
Data Source
AI summary
A memory controller includes driver circuitry, which includes main driver circuitry and hold driver circuitry. The main driver circuitry and hold driver circuitry are connected to an output node. The main driver circuitry comprises driver slice circuitries and outputs a first output signal to the output node based on a first input signal and a second input signal and a number of activated driver slice circuitries. The hold drive circuitry receive the first input signal and outputs a second output signal. The second output signal is delayed with reference to the first output signal by a first delay amount.