Boosted Switch Driver Circuit With Level Shifting for Fast RF Clock Edges
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Solution Overview
Problem
Designing boosted switch drivers for high-speed signal switching, especially in RF ADCs, is challenging due to physical constraints and the need for optimal performance in terms of cost, quality, and robustness.
Innovation Solution
The proposed solution involves a boosted switch driver circuit with two branches, one including a P-type transistor and the other an N-type transistor, with a level shifter circuit in the branch of the P-type transistor. This configuration allows for level-shifting of the input clock signal, enabling an output voltage swing beyond the core supply rails and providing careful control over the maximum and minimum signal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the supply voltage is increased to achieve larger output swing, then the output amplitude is improved, but the power consumption increases
Solution Approach 1:
The patent changes the voltage parameter by introducing a boosted voltage rail (VBB) that exceeds the core supply voltage. This allows the output swing to be extended beyond the normal supply rails, achieving larger output amplitude without proportionally increasing the main supply voltage and thus controlling power consumption.
Solution Approach 2:
The voltage supply system is segmented into multiple independent voltage rails: core supply voltage (VDD/VSS) for basic operation and a separate boosted voltage rail (VBB/VBBS) for extended swing. This segmentation allows independent optimization of power consumption and output amplitude by selectively activating the boosted rail only when extended swing is needed.
2Reliability
If the circuit is designed to compensate for PVT and mismatch variations, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The circuit employs feedback mechanisms where the boosted voltage generation and the switching operation are interconnected. The switched capacitor network automatically adjusts the voltage boost level based on the operating conditions, providing implicit PVT compensation without requiring separate complex control circuits.
Solution Approach 2:
The boosted switch driver circuit is designed to self-compensate for PVT variations through its inherent switched capacitor topology. The circuit automatically adjusts its operation to maintain performance across process, voltage, and temperature variations without external intervention or complex additional compensation circuits.
3Productivity
If the output voltage swing is extended beyond core supply rails, then the dynamic range is improved, but the device complexity increases
Solution Approach 1:
The patent merges the voltage boosting function with the switch driver operation into a single integrated circuit. The switched capacitor network simultaneously performs signal switching and voltage boosting, eliminating the need for separate voltage multiplier circuits and reducing overall device complexity despite achieving extended output swing.
Solution Approach 2:
The switched capacitor network performs multiple functions: it acts as the switching element, generates the boosted voltage rail, and provides level shifting capability. This multi-functionality achieves extended dynamic range without proportionally increasing circuit complexity, as a single circuit block accomplishes what would otherwise require multiple separate components.
Data Source
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AI summary
An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.