Booster Circuit Charge Backflow Reduction
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Solution Overview
Problem
Conventional booster circuits for flash memories experience a decrease in boosting efficiency due to immediate backflow of charge after the clock signal transitions, leading to reduced operating margins and efficiency in data read and rewrite operations.
Innovation Solution
A booster circuit design utilizing multiple (M≧4) boosting cell lines arranged in parallel, with each stage configured to operate in synchronization with different phase clock signals, featuring a charge transfer transistor that can be set to a non-conductive state without complex clock control, reducing backflow and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional booster circuit uses simple clock signal control for the charge transfer transistor, then the device complexity is reduced, but charge backflow occurs immediately after boosting, decreasing boosting efficiency
Solution Approach 1:
The patent applies preliminary action by setting the charge transfer transistor to the non-conductive state in advance before the boosting operation completes. This prevents charge backflow before it can occur, maintaining boosting efficiency without requiring complex clock control. The transistor is proactively switched off based on timing relative to the clock signal transitions.
Solution Approach 2:
The patent implements dynamics by making the charge transfer transistor's conductivity state changeable and controllable. The transistor transitions between conductive and non-conductive states based on the clock signal phases, allowing the circuit to dynamically adapt its behavior to prevent charge backflow while maintaining simplicity in the control mechanism.
2Ease of operation
If the charge transfer transistor remains conductive after boosting, then ease of operation is maintained, but charge flows backward to the preceding stage, reducing boosting efficiency
Solution Approach 1:
The patent applies periodic action by synchronizing the charge transfer transistor's state changes with the periodic clock signal. The transistor is set to non-conductive state during specific phases of the clock cycle (when the clock signal transitions from low to high), creating a periodic control pattern that prevents charge backflow while maintaining operational simplicity through clock signal synchronization.
3Loss of energy
If multiple boosting cell lines are used in parallel, then boosting efficiency is maintained, but the area required for the booster circuit increases
Solution Approach 1:
The patent applies segmentation by dividing the booster circuit into multiple parallel boosting cell lines (M≥4). Each cell line operates independently with its own charge transfer transistor and boosting capacitor, allowing the circuit to maintain high boosting efficiency through distributed operation while the overall area increase is managed by the efficient packing and parallel architecture of the segmented cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces charge backflow and maintains high boosting efficiency, optimizing the operating margin and reducing the area required for the booster circuit, even in twin-well CMOS processes.
Implementation Method 1
a boosting capacitor which boosts the output of a charge transfer cell
Implementation Method 2
a charge transfer transistor connected between an input terminal and the output terminal of the boosting cell
Data Source
AI summary
In a booster circuit which is operated with a two-phase clock and in which a plurality of (M≧4) lines of boosting cells constitute a unit, a boosting cell in the K-th line (1≦K≦M) is controlled, depending on the voltage of the input terminal of a boosting cell in the KA-th line (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). As a result, a charge transfer transistor can transition from the conductive state to the non-conductive state before a clock input to the boosting cell in the K-th line transitions from low to high and then boosting operation is performed. As a result, the backflow of charge via the charge transfer transistor can be reduced or prevented.