Booster Circuit Gate Voltage Control for Recovery Speed
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Solution Overview
Problem
Conventional booster circuits face inefficiencies and prolonged recovery times when transitioning between modes, particularly when using low power supply voltages, due to excessive gate voltage pulling and insufficient equalization, leading to increased current consumption and prolonged recovery times.
Innovation Solution
Incorporating a pull-out lower limit voltage supply section in the reset circuit to ensure the gate voltage of the charge transfer transistor remains above a certain threshold, preventing excessive pulling and overcharging, and utilizing the output voltage or power supply voltage as the pull-out lower limit voltage to simplify the circuit and enhance recovery speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate voltage is pulled out to reset the charge transfer transistor during mode transition, then the transistor can be turned off to prevent charge backflow, but the gate voltage may be pulled out excessively causing the transistor to remain off and prolonging recovery time
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the pull-out voltage level based on operational mode. During mode transition, the reset circuit pulls the gate voltage to a specific level that is sufficient to turn off the charge transfer transistor but not excessively low to cause prolonged recovery. This controlled parameter adjustment resolves the contradiction between ensuring reliable charge transfer control and minimizing recovery time.
2Reliability
If the gate voltage is pulled out to ensure complete charge transfer transistor turn-off, then charge backflow is prevented, but current consumption increases due to excessive voltage pulling
Solution Approach 1:
The patent optimizes the pull-out voltage parameter to achieve the minimum necessary level for reliable transistor turn-off without excessive voltage reduction. By carefully controlling the reset voltage level and timing, the circuit prevents charge backflow while minimizing the current consumption associated with voltage pulling operations.
3Use of energy by moving object
If the gate voltage is not pulled out sufficiently during mode transition, then current consumption is reduced, but the charge transfer transistor may not turn off completely leading to charge backflow
Solution Approach 1:
The patent establishes an optimal pull-out voltage parameter that ensures complete transistor turn-off while minimizing current consumption. The reset circuit is designed to pull the gate voltage to a precise level that guarantees reliable charge transfer control without unnecessary energy waste, resolving the contradiction between current consumption and charge transfer reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the boosting operation, reduces current consumption, and shortens recovery time by preventing excessive gate voltage pulling and ensuring efficient charge transfer, thereby improving the overall performance of the booster circuit.
Implementation Method 1
The gate voltage boosting capacitor C1 equalizes the gate voltage Vg of the charge transfer transistor M3 with the drain voltage Vd and then pumps up the gate voltage Vg
Implementation Method 2
The output-voltage capacitor C2 turns on the charge transfer transistor M3 in accordance with the clock CLKS and then pumps up a source voltage Vs
Implementation Method 3
The charge transfer transistor M3 transfers charges from the preceding stage to the following stage
Data Source
AI summary
A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.