Booster Circuit Adjusts Global Bit Line Signal Edges
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices changes, affecting operating voltages and overall IC performance.
Innovation Solution
A memory circuit design that includes a set of memory cells and a local input output (LIO) circuit coupled to a global bit line. The LIO circuit features a sense amplifier, a driver circuit, and a booster circuit that adjusts the global bit line signal in response to a delayed signal, enhancing read operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor IC is made smaller and more complex, then the integration density is improved, but the resistance of conductive lines changes affecting operating voltages and performance
Solution Approach 1:
The patent changes the voltage parameter by introducing a booster circuit that generates a boosted voltage signal higher than the normal operating voltage. This compensates for voltage drops caused by increased line resistance in scaled-down devices, maintaining reliable operation despite higher integration density.
Solution Approach 2:
The booster circuit acts as an intermediary between the memory cell and the read amplifier, providing an enhanced voltage signal that overcomes the resistance issues in scaled conductive lines. This intermediate voltage boosting ensures sufficient signal levels reach the read amplifier for reliable data retrieval.
2Productivity
If the resistance of conductive lines increases due to scaling, then the integration density is improved, but the signal strength and operating performance deteriorate
Solution Approach 1:
The patent modifies the voltage parameter by generating a boosted voltage signal that is higher than the normal operating voltage. This compensates for signal degradation caused by increased line resistance, ensuring adequate signal strength reaches the read amplifier despite scaling effects.
3Reliability
If a booster circuit is added to compensate for voltage drops, then the operating voltage stability is improved, but the device complexity increases
Solution Approach 1:
The booster circuit is implemented as a separate, modular component within the memory circuit, distinct from the core memory cell array and read amplifier. This segmentation allows the voltage boosting function to be added without fundamentally redesigning the entire memory architecture, managing complexity through functional separation.
4Productivity
If the conductive lines are made thinner to increase density, then the integration density is improved, but the resistance increases affecting performance
Solution Approach 1:
The patent changes the voltage parameter by introducing a boosted voltage signal that compensates for the increased resistance in thinner conductive lines. This maintains adequate signal levels and transmission speed despite the reduced line dimensions required for higher density.
Data Source
AI summary
A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a driver circuit configured to generate a global bit line signal in response to a first signal or an inverted first signal, and a booster circuit coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal. The booster circuit includes a first inverter configured to generate a second signal in response to the global bit line signal, a delay circuit configured to generate a delayed second signal in response to the second signal, and a second inverter configured to generate a third signal in response to the delayed second signal.