Booster Circuit Parallel Last Stage Voltage Stress Reduction

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Solution Overview

Problem

Existing booster circuits for non-volatile memories, such as EEPROMs, face inefficiencies in charge transfer due to diode-connected NMOS transistors, leading to increased threshold voltage and reduced charge transfer efficiency, along with the need for additional switching elements and memory to control booster cell rotation, which complicates the design and increases stress on boost capacitors.

Innovation Solution

A booster circuit design where multiple booster cells in the last stage are connected in parallel, allowing for switching based on the boosting operation to reduce voltage stress and optimize charge transfer transistor design, eliminating the need for additional switching elements in intermediate stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If diode-connected NMOS transistors are used as charge transfer transistors in booster cells, then the circuit can be simplified, but the threshold voltage increases due to body effect, reducing charge transfer efficiency

Engineering Contradiction:

Improvecircuit complexityVSAvoidcharge transfer efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The booster circuit is divided into multiple stages with different charge transfer transistor configurations. Early stages use diode-connected NMOS transistors for simplicity, while the last stage uses optimized charge transfer transistors for high efficiency, allowing each segment to be designed for its specific function

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different transistor configurations are applied to different stages based on their specific requirements. The last stage uses specially designed charge transfer transistors with optimized dimensions and connections to minimize body effect and maximize charge transfer efficiency, while other stages use simpler configurations

Inventive Principle:

Principle #3Local quality

2Reliability

If booster cells are rotated to equalize stress on boost capacitors, then capacitor stress is balanced, but additional switching elements and control memory are required, increasing device complexity

Engineering Contradiction:

Improvecapacitor stress distributionVSAvoidswitching elements and control memory

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The rotation control functionality is extracted from the intermediate stages and implemented only in the last stage. This eliminates the need for rotation control switches and memory in earlier stages, reducing overall device complexity while still achieving stress equalization through the last stage's control mechanism

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of rotating all booster cells to equalize stress, the invention keeps most cells fixed and only rotates the last stage cells. This inverted approach achieves the same stress equalization goal with fewer switching elements and less control logic

Inventive Principle:

Principle #13The other way round (Inversion)

3Duration of action of moving object

If multiple booster cells in the last stage are connected in parallel with switching, then voltage stress time is reduced by half, but switching control is required

Engineering Contradiction:

Improvevoltage stress durationVSAvoidswitching control

Core Design Contradiction:

Duration of action of moving objectVSDevice complexity

Solution Approach 1:

Multiple booster cells in the last stage are merged in parallel configuration, sharing common input and output terminals. This allows the cells to be activated alternately, reducing the voltage stress duration on each cell while the switching control is integrated into the existing booster cell structure

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the time period of voltage stress on the most stressed booster cells by half, enabling optimal design of charge transfer transistors and reducing the frequency of element usage, thereby enhancing charge transfer efficiency and simplifying the circuit architecture.

Implementation Method 1

a boost capacitor connected between the input terminal and a clock terminal

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

charge transfer transistors 511, 521, 531, and 541 formed of diode-connected NMOS transistors

Methodology Applied

Scientific EffectField effect transistor conduction: Conduction (electrical)

Data Source

PatentUS10157645B2Booster circuit and non-volatile memory including the same

Publication Date: 2018.12.18 ABLIC INC

AI summary

To obtain a booster circuit capable of reducing voltage stress applied to a booster cell, provided is a booster circuit including a plurality of booster cells connected in series. Each of the plurality of booster cells includes a charge transfer transistor connected between an input terminal and an output terminal, and a boost capacitor connected between the input terminal and a clock terminal. Among the plurality of booster cells, a plurality of booster cells at least in a last stage are connected in parallel so that the plurality of booster cells connected in parallel are connected to a booster cell in a previous stage of the last stage by switching the plurality of booster cells in the last stage in accordance with a boosting operation.