Booster Circuit N Well Potential Control
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Solution Overview
Problem
Conventional booster circuits for flash memories and CMOS processes face inefficiencies due to parasitic capacitance and increased layout area, resulting in decreased boost efficiency and charge transfer efficiency, as the source and N well of the charge transfer transistor are connected, leading to unnecessary charge discharge and substrate biasing effects.
Innovation Solution
The booster circuit design fixes the potential of the N well to the input or output potential of the boosting cell stage, reducing charge transfer between the N well and substrate, and employs analog comparison circuits to control well potentials, thereby reducing parasitic capacitance and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the source and N well of the charge transfer transistor are connected to the same potential, then the substrate biasing effect is suppressed and charge transfer efficiency is improved, but parasitic capacitance causes unnecessary charge discharge and reduces boost efficiency
Solution Approach 1:
The patent segments the N well connection by introducing separate N well regions (first N well and second N well) that are independently controlled. The first N well is connected to the source potential while the second N well is connected to a fixed potential, allowing independent optimization of charge transfer and parasitic capacitance effects.
Solution Approach 2:
The patent introduces an intermediate potential control mechanism using analog comparison circuits that compare the source potential with a reference potential and adjust the N well potential accordingly. This intermediary control system optimizes the balance between suppressing substrate biasing effects and minimizing parasitic capacitance charge discharge.
2Productivity
If the N well potential is fixed to the source potential, then substrate biasing effect is suppressed, but parasitic capacitance increases leading to larger layout area
Solution Approach 1:
The patent divides the N well structure into multiple independently controllable regions, allowing selective connection to different potentials. This segmentation reduces the total parasitic capacitance while maintaining the beneficial substrate biasing suppression in critical regions.
Solution Approach 2:
The patent dynamically changes the N well potential parameter based on operating conditions. By using analog comparison circuits to adjust the N well potential between fixed and source-potential modes, the system optimizes the balance between charge transfer efficiency and parasitic capacitance effects.
3Reliability
If separate N wells are provided for each boosting cell, then substrate biasing control is improved, but layout area increases
Solution Approach 1:
The patent merges multiple N well regions into shared common N wells that serve multiple boosting cells. The first N well and second N well are shared among adjacent boosting cells, reducing the total number of separate N wells while maintaining independent potential control through shared analog comparison circuits.
Solution Approach 2:
The patent implements universal N well control structures where the same N well regions and control circuits serve multiple functions across different boosting cells. The analog comparison circuits and N well regions are designed to be multi-functional, controlling substrate biasing for multiple cells simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces current consumption, improves boost efficiency, and stabilizes the boosting operation by minimizing charge transfer and substrate biasing effects, while also reducing the layout area and noise interference.
Implementation Method 1
a parasitic capacitance formed by the N well 908 is charged and discharged by voltage transition widths of the clock signals CLK1 and CLK2
Implementation Method 2
909 indicates a parasitic diode between the P well 907 and the N well 908
Data Source
AI summary
A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared.