Booster Circuit Voltage Ripple Reduction via Segmented Charge Pump
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Solution Overview
Problem
Booster circuits in semiconductor memory devices face challenges in reducing voltage ripples across a wide range without increasing circuit area, particularly in maintaining desired output voltages while minimizing noise and ripple effects on write/read operations.
Innovation Solution
The booster circuit incorporates a charge pump circuit with series-connected transistors and capacitors, along with a clock processing circuit featuring NMOS transistors and inverters, which regulate the clock signal to manage voltage boosting and ripple reduction, ensuring stable output voltages across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the booster circuit uses conventional charge pump design, then voltage boosting function is achieved, but output voltage ripple increases
Solution Approach 1:
The charge pump circuit is divided into multiple stages with separate pumping capacitors (first pumping capacitor and second pumping capacitor) that operate at different clock phases. This segmentation allows independent optimization of each stage to reduce overall output voltage ripple while maintaining the voltage boosting function.
Solution Approach 2:
Different pumping capacitors are designed with different capacitance values and connected to different clock signal phases (CLK and /CLK). This local differentiation optimizes the charging and discharging characteristics at each stage, reducing voltage ripple locally and collectively improving overall output stability.
2Object-generated harmful factors
If the booster circuit increases circuit area to reduce ripple, then output voltage stability improves, but device area increases
Solution Approach 1:
The circuit uses periodic clock signals (CLK and /CLK) to control the charging and discharging of pumping capacitors in alternating phases. This periodic operation allows the same capacitor to serve multiple functions over time, reducing the total capacitor size needed compared to continuous operation designs, thereby reducing circuit area while maintaining ripple reduction performance.
Solution Approach 2:
Each pumping capacitor serves multiple functions: voltage boosting, ripple filtering, and clock signal conditioning. By making components multi-functional, the design reduces the total number of components needed, thereby reducing circuit area while achieving effective ripple reduction.
3Adaptability or versatility
If the booster circuit maintains desired output voltage across wide range, then operational flexibility improves, but circuit complexity increases
Solution Approach 1:
The circuit uses dynamic clock signal control where the phase and timing of CLK and /CLK signals are optimized to achieve different output voltage levels. This dynamic control allows the same hardware configuration to adapt to different voltage requirements without adding complex control circuits, maintaining operational flexibility while limiting complexity growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces voltage ripples and maintains desired output voltages across a wide range, preventing circuit area expansion and ensuring stable write/read operations, even at low output voltages, by utilizing NMOS transistors to maintain voltage levels and control boosting speeds.
Implementation Method 1
a plurality of capacitors each of which is connected to a channel electrode of a corresponding one of the transistors
Data Source
AI summary
A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.