Booster Word Line for SRAM Voltage Profile
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Solution Overview
Problem
As memory structures and word lines in SRAM devices become smaller, they experience undesirable voltage profiles and increased resistance, degrading performance due to lack of space for larger metal structures and design constraints.
Innovation Solution
The introduction of additional thicker and wider booster word lines, formed in a different metal layer or with a different metal type, which are connected to the existing word lines to improve the voltage profile and reduce resistance, allowing for charging from both ends of the selected word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures and word lines are made smaller to increase density, then storage capacity is improved, but voltage profile degrades and resistance increases
Solution Approach 1:
The patent introduces a second metal layer (M2) above the first metal layer (M1) to create a three-dimensional wire structure. This vertical stacking approach allows the word line to extend in the Z-dimension, effectively increasing the conductive path cross-section without expanding the planar footprint, thereby maintaining high density while improving voltage profile and reducing resistance.
Solution Approach 2:
The patent employs a composite wire structure combining two different metal layers (M1 and M2) with potentially different material properties. This composite approach allows optimization of electrical characteristics by combining materials with complementary properties, achieving both low resistance and good voltage profile in a compact structure.
2Quantity of substance
If memory structures and word lines are made smaller to increase density, then storage capacity is improved, but resistance increases
Solution Approach 1:
By stacking metal layers vertically in the Z-dimension, the patent increases the effective cross-sectional area of the word line without increasing planar dimensions. This dimensional transition reduces resistance while preserving the compact footprint required for high storage density.
Solution Approach 2:
The patent changes the geometric parameters of the word line by introducing a vertical component through multiple metal layers. This parameter change (from planar to three-dimensional structure) fundamentally alters the resistance characteristic while maintaining compatibility with scaled-down memory cell dimensions.
3Reliability
If metal word line structure is increased to improve voltage profile, then performance is improved, but space availability decreases
Solution Approach 1:
The patent resolves the space conflict by utilizing the vertical Z-dimension for metal layer stacking. This allows the word line structure to be enhanced in the vertical direction while maintaining constant planar footprint, effectively decoupling performance improvement from area consumption.
Solution Approach 2:
The patent implements a nested structure where the second metal layer (M2) is positioned above and nested within the vertical profile defined by the first metal layer (M1) and intervening dielectric. This nesting approach maximizes space utilization by stacking conductive elements vertically rather than expanding horizontally.
Data Source
AI summary
A semiconductor device is provided. The semiconductor includes a plurality of memory cells arranged in rows and columns. The device further includes a plurality of primary word lines, each being connected to a first plurality of memory cells arranged in a row and a plurality of bit line pairs, each being connected to a second plurality of memory cells arranged in a column. The device further includes a word line driver circuit operative to select a first primary word line of the plurality of primary word lines and charge the selected first primary word line from a first end and a secondary word line operative to charge the selected first primary word line from a second end.