Boosting Circuit Back Gate Control for Latch-Up Prevention

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Solution Overview

Problem

Existing boosting circuits face efficiency degradation due to latch-up and reactive current issues during initial charging and standby periods, as parasitic bipolar transistors are turned on when the base voltage falls below the emitter voltage, especially in transition phases.

Innovation Solution

A boosting circuit design where the back gate of charging and discharging MOS transistors is connected to a common node, with different voltages applied during charging and discharging operations, utilizing a schottky-barrier diode to maintain the back gate voltage above the emitter voltage, preventing parasitic bipolar transistor activation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the back gate voltage is not controlled during transition periods, then the circuit operation is simple, but the parasitic bipolar transistor turns on causing latch-up and reactive current

Engineering Contradiction:
Improveprevention of latch-up and reactive currentVSAvoidcontrol mechanism for back gate voltage
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A diode-connected MOS transistor is introduced as an intermediary component between the power supply and the back gate of the charging/discharging MOS transistors. This intermediary automatically maintains the back gate voltage above the emitter voltage of the parasitic bipolar transistor during transition periods (initial charging and standby), preventing parasitic bipolar transistor activation without requiring complex control circuits. The diode-connected structure provides automatic voltage regulation through its inherent electrical characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If separate back gate control is implemented for charging and discharging MOS transistors, then parasitic bipolar transistor activation is prevented, but the device complexity increases

Engineering Contradiction:
Improveprevention of parasitic bipolar transistor activationVSAvoidnumber of control circuits
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The back gate control for both the charging MOS transistor and the discharging MOS transistor is merged into a single unified control mechanism. Instead of implementing separate control circuits for each transistor, the patent applies the same diode-connected MOS transistor structure to both devices, sharing the control functionality. This merging approach prevents parasitic bipolar transistor activation in both charging and discharging operations while minimizing device complexity through component sharing and structural simplification.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents parasitic bipolar transistor activation during all operation periods, thereby preventing latch-up and reactive current, ensuring efficient operation throughout the initial charging, boosting, and standby phases.

Implementation Method 1

utilizing a schottky-barrier diode to maintain the back gate voltage above the emitter voltage, preventing parasitic bipolar transistor activation

Methodology Applied
Scientific EffectSchottky-barrier diode effect: Diode

Data Source

PatentUS7633332B2Boosting circuit and boosting method
Publication Date: 2009.12.15 RENESAS ELECTRONICS CORP
  • US7633332B2 patent drawing
  • US7633332B2 patent drawing
  • US7633332B2 patent drawing

AI summary

A boosting circuit includes a boosting capacitor to which an input voltage is applied; a smoothing capacitor to which a boosted voltage is applied; a discharging MOS transistor configured to connect said boosting capacitor and said smoothing capacitor in a discharging operation during a boosting operation period such that charge stored in said boosting capacitor is discharged to said smoothing capacitor; and a charging MOS transistor configured to apply the input voltage to said boosting capacitor in a charging operation during the boosting operation period to charge up said charging capacitor. A back gate of said charging MOS transistor and a back gate of said discharging MOS transistor are connected to a common node, and said common node is connected to different voltages in the charging operation and the discharging operation.