Multi-Sequence Boosting Circuit for Charge Backflow Suppression
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Solution Overview
Problem
Conventional boosting circuits experience a decrease in efficiency due to backflow of charges via charge transfer transistors immediately after boosting, which affects the overall performance of flash memory devices and analog circuits.
Innovation Solution
A boosting circuit with multiple parallel sequences and stages, utilizing a charge transfer transistor that remains non-conductive during boosting operations, and a state control unit to manage the transistor's state based on the output voltage of preceding boosting cells, preventing backflow and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the charge transfer transistor is controlled to remain non-conductive during boosting operations, then boosting efficiency is improved, but device complexity increases
Solution Approach 1:
The charge transfer transistor is pre-configured to be non-conductive before boosting operations begin. The control mechanism proactively sets the transistor state in advance to prevent charge backflow, rather than reacting after the problem occurs. This preliminary action ensures boosting efficiency is maintained from the start of each boosting cycle.
Solution Approach 2:
A control mechanism acts as an intermediary between the clock signal and the charge transfer transistor. This intermediary component receives timing information and translates it into appropriate control signals that switch the transistor between conductive and non-conductive states, managing the complexity centrally rather than through distributed control.
2Duration of action of moving object
If multiple parallel sequences and stages are used, then charge transfer time is increased, but layout area increases
Solution Approach 1:
The boosting circuit is divided into multiple parallel sequences (first sequence, second sequence, etc.) and stages (first stage, second stage, etc.). Each sequence contains multiple boosting cells arranged in stages. This segmentation allows charge transfer to occur simultaneously across multiple paths, extending the effective charge transfer time without requiring a single large transistor, thereby managing layout area more efficiently.
Solution Approach 2:
Instead of extending charge transfer time through a single long path (one dimension), the circuit uses multiple parallel sequences arranged in a two-dimensional grid structure. This dimensional approach allows simultaneous charge transfer across multiple paths, achieving extended effective transfer time while maintaining compact layout area through spatial parallelism.
3Area of stationary object
If the charge transfer transistor size is reduced, then layout area is minimized, but charge transfer capability decreases
Solution Approach 1:
The charge transfer function is segmented across multiple smaller transistors arranged in parallel sequences and stages, rather than using a single large transistor. Each transistor in the sequence handles a portion of the charge transfer task, allowing the overall system to achieve high charge transfer capability while each individual transistor maintains a small size for compact layout.
Solution Approach 2:
Multiple small transistors in parallel sequences are combined to achieve the equivalent charge transfer capability of a single large transistor. The parallel arrangement of first sequence, second sequence, and subsequent sequences with multiple stages each creates a collective transfer capability that matches or exceeds larger single-transistor designs while occupying less layout area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses charge backflow, improves boosting efficiency, and allows for increased charge transfer time without increasing the layout size of the charge transfer transistor, while maintaining a simple clock signal and avoiding parasitic bipolar generation.
Implementation Method 1
a boosting capacitance having two ends, one end being connected to the output terminal of the boosting cell, and the other end receiving a clock signal corresponding to the boosting cell
Implementation Method 2
a charge transfer transistor connected between the input terminal and the output terminal of the boosting cell, and for transferring charges from the input terminal to the output terminal when the charge transfer transistor is in a conductive state
Data Source
AI summary
A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented.