Boot Code Clone in Single Flash Memory

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Solution Overview

Problem

Conventional computer systems require two separate flash memories for DualBIOS or TwinBIOS systems to manage and update boot code, which occupies valuable space and resources, especially in space-constrained devices like wearable devices and IoT devices.

Innovation Solution

A memory device and method that utilizes a single non-volatile memory with two portions, allowing for dual-area updates by switching between them for reading and writing boot code, ensuring continuous operation during updates without the need for separate flash memories.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two separate flash memories are used for DualBIOS or TwinBIOS systems, then system reliability is improved, but device complexity and space consumption increase

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides a single flash memory into two distinct portions: a first portion for storing current boot code and a second portion for storing updated boot code. This segmentation allows the system to maintain dual-boot-code functionality while using only one physical flash memory device, thereby improving reliability without increasing device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges the functionality of two separate flash memories into a single flash memory device by implementing logical separation through status logic and address mapping. The control circuitry manages both portions within one device, combining storage resources while maintaining the reliability benefits of having separate boot code areas.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If two separate flash memories are used for DualBIOS or TwinBIOS systems, then system reliability is improved, but area occupied on motherboard increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidarea occupied on motherboard
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines what would traditionally require two separate flash memory physical devices into a single flash memory device. By using internal status logic and address mapping mechanisms, the system achieves dual-boot-code functionality within one physical component, thereby maintaining system reliability while reducing the area occupied on the motherboard.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single flash memory device is designed to perform multiple functions: storing current boot code, storing updated boot code, and supporting boot operations from either portion. This multi-functionality eliminates the need for dedicated separate flash memories, reducing overall space requirements while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If boot code is updated in place without backup, then space is saved, but risk of system failure increases

Engineering Contradiction:
Improvespace usageVSAvoidrisk of system failure
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the flash memory into first and second portions with distinct roles during the update process. The first portion holds the current working boot code while the second portion receives updated boot code. This segmentation ensures that even during updates, a valid boot code is always available, reducing system failure risk while using only one physical device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary validation of updated boot code before switching to it. The status logic verifies the integrity and validity of the updated boot code in the second portion before making it active. This preliminary action prevents corrupted or invalid code from causing system failure, maintaining reliability without requiring additional backup devices.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3511826B1System boot code clone
Publication Date: 2022.03.16 MACRONIX INTERNATIONAL CO LTD
  • EP3511826B1 patent drawingFigure 1
  • EP3511826B1 patent drawingFigure 2
  • EP3511826B1 patent drawingFigure 3

AI summary

A memory device includes a non-volatile memory configured with a block including first and second portions and an address decoder mapping received command addresses to physical addresses of the non-volatile memory. The memory device includes control circuitry maintaining a current status of the first portion and the second portion and implementing an update operation, including responsive to receiving a write command sequence to the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information, and upon completion of the updating, changing the current status to indicate that the selected one of the first and second portion is the current area.