Boot Control Unit Dual-Bus Transfer for Automotive Start-Up
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Solution Overview
Problem
Conventional computing devices, such as those using the Intel® Centrino® Atom™ platform, experience significant start-up delays due to the oscillation build-up time of real-time clock quartz oscillators, which is excessive in automotive environments, leading to undefined behavior and failure to meet stringent automotive application requirements.
Innovation Solution
The computing device employs a system management controller (SMC) to generate a clock signal at a higher frequency, reducing oscillation build-up time, and utilizes a boot control unit with multiple interfaces to efficiently transfer control instructions via both low pin count (LPC) and high-speed PCIe buses, allowing for earlier processing of reset signals and faster initial program load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a real-time clock quartz oscillator is used to generate a clock signal for reset processing, then the CPU can process reset signals, but the oscillation build-up time of 800 ms or more causes significant start-up delays
Solution Approach 1:
The patent applies preliminary action by using a fast oscillator to generate a clock signal before the quartz oscillator is fully stabilized. The boot control unit captures the reset signal and processes boot instructions using this preliminary clock signal, allowing the system to start up faster than waiting for the quartz oscillator to stabilize completely.
Solution Approach 2:
The patent segments the boot process into two phases: a first boot phase using a fast oscillator for rapid initialization, and a second boot phase using the stabilized quartz oscillator clock signal. This segmentation allows the system to achieve fast start-up while maintaining reliable reset processing.
2Reliability
If the reset signal is held until the RTC clock signal build-up time elapses, then undefined or erratic behavior is prevented, but the start-up delay is extended
Solution Approach 1:
The system performs preliminary clock signal generation using a fast oscillator before the quartz oscillator stabilizes. The reset signal is captured and processed during this preliminary phase, allowing the system to reach a stable state faster than waiting for the quartz oscillator to complete its build-up time.
Solution Approach 2:
The patent changes the clock signal frequency parameter by using a fast oscillator (higher frequency) during the initial boot phase instead of waiting for the low-frequency quartz oscillator to stabilize. This parameter change enables faster processing while maintaining system stability through proper signal sequencing.
3Device complexity
If control instructions are transferred via the relatively slow low pin count (LPC) bus, then the boot process is simple, but the initial program load time is extended
Solution Approach 1:
The patent segments the control instruction transfer into two parts: a first part transferred via the LPC bus for simplicity, and a second part transferred via a high-speed bus (such as PCI or PCI Express) for faster loading. This segmentation allows the system to maintain boot simplicity while achieving fast initial program load times.
Solution Approach 2:
The patent adds another dimension to the boot control structure by introducing a high-speed bus interface alongside the existing LPC bus. This dimensional expansion allows the system to leverage both simple and high-speed transfer paths, optimizing both complexity and performance.
Data Source
AI summary
A computing device is provided that includes a computing unit, which has a working memory and a processing unit, and a boot memory having control instructions for operating the computing device. The control instructions are stored in boot memory and are to be transferred to the computing unit at start-up of the computing device. A boot control unit is connected to the computing unit by at least a first and a second interface and connected to the boot memory by a third interface. The boot control unit is configured to transfer a first part of the control instructions from the boot memory via the first interface to the computing unit and to transfer a second part of the control instructions from the boot memory via the second interface to the computing unit.