Boot-Time Memory Die Crack Detection in Integrated Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit (IC) devices with memory chiplets or High-Bandwidth Memory (HBM) stacks face challenges in detecting damage during boot, as they are often inaccessible for die crack testing after being integrated into customer systems, leading to potential runtime faults and data corruption.
Innovation Solution
Incorporating die crack testing into the boot process of IC devices, allowing for real-time detection of memory damage during boot, using a dedicated test port, which enables the detection of physical damage during the boot process, using a dedicated test port, which eliminates the need for physical access to the JTAG port, which enables the detection of physical damage during the boot process, using a dedicated test port, which eliminates the need for physical access to the JTAG port, which enables the detection of physical damage during the boot process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die crack testing is performed using traditional JTAG port methods, then physical access is required which limits testing to pre-deployment scenarios, but the ability to detect damage after integration is lost
Solution Approach 1:
The system performs self-diagnosis by executing die crack tests automatically during the boot process without requiring external testing equipment or physical access to JTAG ports. The boot processor itself initiates and collects test results, enabling the device to self-verify its integrity after integration into customer systems.
Solution Approach 2:
The die crack testing is performed preliminarily during the boot process before the system enters normal operation. This early detection approach allows damage to be identified at the first opportunity after deployment, preventing undetected faults from causing data corruption during runtime.
2Reliability
If traditional post-deployment testing methods are used, then physical access to JTAG ports is required, but this becomes impossible after devices are integrated into customer systems
Solution Approach 1:
The device performs its own testing without requiring external testing infrastructure. The boot processor executes die crack tests on memory devices autonomously, eliminating the need for customer systems to provide physical access to JTAG ports or specialized testing equipment.
Solution Approach 2:
The boot processor serves multiple functions: it initializes the system, loads the operating system, and simultaneously performs die crack testing on memory devices. This multi-functionality allows testing capability to be integrated into the existing boot infrastructure without adding separate dedicated testing hardware.
3Productivity
If die crack testing is not performed during boot, then devices can be delivered without runtime detection capability, but potential faults and data corruption go undetected
Solution Approach 1:
The die crack testing function is merged with the existing boot process. Instead of adding a separate testing phase that would delay device delivery, the testing operations are combined with the mandatory boot sequence, so that devices must pass both boot and testing simultaneously, enabling delivery without compromising reliability.
Solution Approach 2:
Testing is performed preliminarily during boot before the system enters production use. This ensures that any damage is detected early, preventing faulty devices from being deployed into service where they could cause data corruption or system failures.
Data Source
AI summary
Detecting damage to a memory of an integrated circuit device includes initiating a boot process of the integrated circuit device. The boot process is implemented by a boot processor of the integrated circuit device. As part of the boot process, a die crack test of a memory device of the integrated circuit device is initiated. The memory device is coupled to the boot processor. The boot processor receives a result of the die crack test of the memory device during the boot process. The result of the die crack test is stored in a register of the integrated circuit device.