Boot Program Verification Signal Path for Main CPU
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Solution Overview
Problem
Existing information processing apparatuses face challenges in preventing the main CPU from executing a boot program before the completion of verification by a sub CPU, particularly due to incorrect reset signal outputs or malicious modifications, which can lead to execution of altered or invalid boot code.
Innovation Solution
An information processing apparatus comprising a storage unit for the boot program, a first control unit for validating the boot program and transmitting a pattern signal upon validation, and a second control unit for executing the boot program only upon receiving this signal, ensuring that the main CPU does not initiate execution until the verification is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the main CPU is kept in reset state by controlling the reset signal from the sub CPU, then the main CPU cannot execute the boot code before verification, but the reset state may be released inappropriately due to solder bridges, dust, or sub CPU failures
Solution Approach 1:
A dedicated verification completion signal line is introduced as an intermediary communication channel between the sub CPU and main CPU. This separate signal path allows the sub CPU to notify the main CPU of verification completion without relying on the reset signal line, thus preventing incorrect reset signals from causing premature execution of unverified boot code.
Solution Approach 2:
The control mechanism is segmented into two independent functions: (1) the reset signal line for keeping the main CPU in reset state during verification, and (2) a separate verification completion signal line for notifying when verification is done. This segmentation allows each signal line to have a dedicated purpose, reducing the risk of one signal interfering with the other's reliability.
2Device complexity
If the reset signal is used to control main CPU execution, then simple control is achieved, but the wiring may be intentionally modified by malicious third parties
Solution Approach 1:
The verification completion signal acts as an intermediary that provides a trusted notification mechanism. Even if the reset signal line is maliciously modified, the separate verification completion signal line remains intact and can prevent execution of tampered boot code by ensuring the main CPU waits for proper verification confirmation.
Solution Approach 2:
The sub CPU performs boot code verification in advance before allowing the main CPU to execute the boot code. The verification completion signal is generated only after successful verification, ensuring that the main CPU executes only verified boot code even if the reset signal line is compromised.
3Speed
If the main CPU executes boot code immediately after reset release, then fast startup is achieved, but execution may occur before verification completion
Solution Approach 1:
The verification completion signal provides feedback from the sub CPU to the main CPU indicating when verification is complete. The main CPU uses this feedback signal to determine the appropriate timing for executing the boot code, ensuring both fast startup (by executing as soon as verification completes) and execution timing accuracy (by waiting for the verification confirmation).
Data Source
AI summary
An information processing apparatus includes a storage unit in which a boot program is stored, a first control unit and a second control unit. The first control unit validates the boot program stored in the storage unit and transmits a pattern signal indicating that the boot program stored in the storage unit is validated. The second control unit executes the boot program stored in the storage unit in accordance with the pattern signal received from the first control unit.