Hardware Squaring via Booth Encoding and Addition Array
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Solution Overview
Problem
Existing methods for squaring numbers in hardware logic are inefficient in terms of hardware size and accuracy, as they require large hardware implementations with significant delays and inaccuracies.
Innovation Solution
The method involves Booth encoding of consecutive bits to generate encoded values, forming truncated strings, and combining these with square and sign bits into an addition array, which reduces the hardware size by almost three-quarters compared to traditional AND-array squarers, while maintaining comparable delay performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional AND-array squarers are used, then accuracy is maintained, but hardware size becomes large
Solution Approach 1:
The patent divides the input number into groups of three consecutive bits and processes each group independently through Booth encoding. This segmentation allows the use of compact lookup tables for each group rather than a large monolithic AND-array, reducing overall hardware size while maintaining accuracy through systematic processing of all segments
Solution Approach 2:
The patent performs Booth encoding on groups of three bits in advance to generate encoded values before the actual squaring operation. This preliminary encoding transforms the input data into a format that enables more efficient hardware implementation, reducing the subsequent hardware requirements while preserving computational accuracy
2Area of stationary object
If hardware size is reduced, then area efficiency improves, but accuracy may deteriorate
Solution Approach 1:
The patent changes the processing parameters by using groups of three bits instead of traditional bit-by-bit or pair-wise processing. This parameter change enables the use of Booth encoding with encoded values ranging from -2 to +2, which optimizes the trade-off between hardware area and accuracy by creating a more efficient representation that reduces area while maintaining faithful rounding
Solution Approach 2:
The patent introduces Booth encoded values as an intermediary representation between the original input bits and the final squaring result. This intermediary encoding step transforms the data into a form that requires less hardware for processing while ensuring accuracy is maintained through the systematic reconstruction of the square from the encoded components
3Area of stationary object
If Booth encoding is applied to groups of three bits, then hardware area is reduced by almost three-quarters, but implementation complexity increases
Solution Approach 1:
The patent merges multiple operations into unified processing units: Booth encoding, truncated string formation, and bit string selection are combined into a single processing stage for each group of three bits. This merging reduces the overall number of discrete hardware components needed, achieving area reduction while managing complexity through functional integration
Data Source
AI summary
Methods of calculating a square of an input number in hardware logic are described. An m-bit number is received and Booth encoding is performed on different groups of three consecutive bits selected from the input to generate an encoded value for each of the groups. For each group, the method comprises forming a truncated string from the input number, generating an updated version of the truncated number and selecting a bit string based on the encoded value, the selected bit string comprising zeros or a left-shifted version of the updated version of the truncated number sign extended to a bit-width of 2m bits. The method further comprises combining the selected bit strings and square and sign bits for each group into an addition array; and summing the bits in the addition array.