Booth-Encoded Multiplier for Resource-Efficient Multiply-Accumulate
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Solution Overview
Problem
Existing processor chips require significant resources and increased costs due to the need for multiple multipliers and accumulation units to perform parallel multiply accumulate operations, which are not efficiently addressed by current multiplication technologies.
Innovation Solution
A computational processing method and multiplier design that utilize Booth-encoding and partial product accumulation to efficiently perform multiplication and multiply accumulate operations, allowing for flexible switching between operations and reducing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple multipliers and accumulation units are implemented to parallelize multiply accumulate operations, then computational capability is improved, but resource consumption increases
Solution Approach 1:
The patent implements a universal multiplier that can perform both standard multiplication and multiple multiply-accumulate operations by using a single multiplier unit with configurable control logic. The multiplier receives multiple first operands and multiple second operands, and through control signals, can accumulate partial products from different operand pairs using the same hardware resources, eliminating the need for separate multipliers and accumulation units for each operation.
Solution Approach 2:
The patent merges the multiplication and accumulation functions into a single integrated unit. The multiplier combines the functionality of multiple multipliers and multiple accumulation units into one device that can handle parallel multiply-accumulate operations by time-multiplexing and space-multiplexing the same hardware resources, thereby reducing overall resource consumption while maintaining computational capability.
2Manufacturing precision
If different multipliers and accumulation units are manufactured for different operations, then operational precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent designs a single universal multiplier that can be manufactured once and used for various multiplication and multiply-accumulate operations. The device includes control logic that configures the same hardware to perform different operations as needed, eliminating the need to manufacture multiple specialized units with different precision characteristics, thereby reducing manufacturing costs while maintaining the required operational precision through software-controlled configuration.
3Adaptability or versatility
If a single multiplier is used for both multiplication and multiply accumulate operations, then resource utilization is improved, but operational complexity increases
Solution Approach 1:
The patent implements dynamic configurability in the multiplier through control signals that can switch the device between multiplication mode and multiply-accumulate mode. The control logic dynamically adjusts the operation based on input signals, allowing the same hardware to adapt to different computational requirements. This dynamic approach manages operational complexity through standardized control interfaces while maximizing resource utilization.
Solution Approach 2:
The patent segments the multiply-accumulate operation into distinct phases that can be managed sequentially by the control logic. The device processes multiple operand pairs through a series of controlled steps, where each phase handles specific aspects of the computation (loading operands, performing multiplication, accumulating results). This segmentation of the operational flow manages complexity by breaking down the versatile functionality into manageable, controlled steps.
Data Source
AI summary
According to an aspect of the disclosure, a computational processing method of multiplier, performed by a processor chip, includes: obtaining, based on n first operands a[k], a first operating part A including BIT(A) bits; obtaining x first encoded data Enc[m] by assigning a lowest bit of consecutive three-bit numbers spanning two adjacent first operands a[k] and a[k−1] to 0, and performing Booth-encoding on the first operating part A; obtaining, based on n second operands b[k], n corresponding second operating parts B[k], each of which has BIT(B) bits; obtaining x partial products based on multiplying the x first encoded data Enc[m] with the n corresponding second operating parts; obtaining an accumulation result based on accumulating the x partial products; obtaining a multiplication result based on truncating the accumulation result; wherein, n, k, x, and m are integers, and wherein 0≤k<n, and 0≤m<x.