Booth Multiplier Partial Product Reduction for Motion Compensation
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Solution Overview
Problem
Existing motion compensation multipliers in codecs like H.264/AVC and VC-1 require a large number of multipliers, leading to increased circuit size and power consumption, despite techniques like discrete cosine transformers and Montgomery multiplication residue arithmetic aiming to reduce these costs.
Innovation Solution
A multiplier and motion-compensating device that utilize Booth's algorithm to reduce the number of partial products by dividing input data into sets of two bits, forming groups of three bits, and selectively adding or subtracting these groups, thereby reducing the number of adders and partial products, and using a Booth encoder to generate code data for cumulative addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Booth's algorithm is applied to motion compensation multipliers, then operation speed is improved, but circuit size increases
Solution Approach 1:
The multiplier is divided into sets of two consecutive bits to generate partial products, and a secondary Booth's algorithm divides the multiplier into groups of three bits. This segmentation reduces the number of partial products that need to be added, thereby reducing the number of adders required and decreasing circuit size while maintaining operation speed
Solution Approach 2:
The invention selectively generates a second partial product only in specific combinations where the high-order bit is 0 or 1 and the third least significant bit is 1. This partial action approach reduces the number of partial products compared to conventional methods, reducing the number of adders and circuit size while still achieving accurate multiplication results
2Measurement precision
If a large number of multipliers are used for filter operation in motion compensation, then processing accuracy is improved, but power consumption increases
Solution Approach 1:
Multiple partial product generation units are merged into a single unit that selectively generates partial products based on input conditions. The adders are also merged and optimized to accumulate partial products efficiently. This consolidation reduces the total number of multipliers and adders required, decreasing power consumption while maintaining processing accuracy through the selective partial product generation strategy
3Speed
If the number of adders is reduced to decrease processing time, then operation speed is improved, but the number of partial products must be reduced
Solution Approach 1:
The multiplier is segmented into groups of three bits using the secondary Booth's algorithm, which reduces the number of partial products from the original bit width to approximately one-third of that. This segmentation allows fewer adders to be used for accumulation, decreasing processing time and improving operation speed
Solution Approach 2:
The invention generates partial products selectively based on specific input conditions (high-order bit is 0 or 1 and third least significant bit is 1). This partial generation approach further reduces the number of partial products that need to be accumulated, allowing for even fewer adders and shorter processing time
Data Source
AI summary
A multiplier includes an operation unit that adds or subtracts a first group selected from a current input data, and a second group selected from a next input data corresponding to the first group to generate an operation result, a Booth's encoder that encodes the operation result according to Booth's algorithm, and generates code data, a partial product generation unit that calculates a partial product from the code data as a first partial product, and calculates, in a case where the first group and the second group are specific combination, a second partial product, and an adder that cumulatively adds an output from the partial product generation unit. The specific combination is a combination in which the highest-order bit of each of the first group and the second group is the same value, and the third least significant bit obtained after the subtraction operation is 1.