Power-Efficient Multiply-Add Arithmetic Circuitry Using Booth Recoding
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Solution Overview
Problem
Arithmetic circuitries face challenges in optimizing the number of Flip Flops (FFs) required for complex arithmetic operations, particularly in multiply-add operations, due to high power consumption and circuit area considerations.
Innovation Solution
The implementation of a multiplier circuitry using radix-4 Booth recoding to divide input terms into blocks, with a saturation logic circuitry to manage overflow and reduce the need for FFs by eliminating the storage of sign bits, allowing for a configuration with fewer FFs and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FFs are inserted to divide arithmetic operation stages, then the arithmetic operation can be completed with proper timing, but power consumption increases
Solution Approach 1:
The patent extracts and removes Flip Flops from the arithmetic operation pipeline, eliminating the need for stage division. The multiplier circuitry is designed to complete the entire multiply-add operation in a single cycle without requiring intermediate storage elements, thereby removing the power-consuming FFs while maintaining operational reliability.
Solution Approach 2:
The patent segments the multiplier operation into parallel processing paths that can be completed simultaneously within one cycle. By organizing the computation to avoid sequential stages requiring FFs, the design achieves proper timing without the power penalty of intermediate storage elements.
2Reliability
If FFs are inserted to divide arithmetic operation stages, then the arithmetic operation can be completed with proper timing, but circuit area increases
Solution Approach 1:
The patent extracts and removes Flip Flops from the arithmetic operation pipeline, eliminating the need for stage division. The multiplier circuitry is designed to complete the entire multiply-add operation in a single cycle without requiring intermediate storage elements, thereby removing the area-consuming FFs while maintaining operational reliability.
3Use of energy by moving object
If the number of FFs is reduced, then power consumption decreases, but the ability to handle complex arithmetic operations may be compromised
Solution Approach 1:
The patent segments the multiplier operation into parallel processing paths that can be completed simultaneously within one cycle. By organizing the computation to avoid sequential stages requiring FFs, the design achieves proper timing without the power penalty of intermediate storage elements.
Solution Approach 2:
The patent employs dynamic recoding techniques that adapt the multiplication process to reduce the number of partial products and simplify the addition tree. This dynamic approach maintains full arithmetic capability while reducing the circuit complexity and eliminating the need for FFs.
Data Source
AI summary
An arithmetic circuitry includes a first processing circuitry, a second processing circuitry, an adder circuitry, and a saturation logic circuitry. The first processing circuitry divides one input term into blocks each of which being divided for each predetermined digit number, to make a least significant bit of each of the blocks overlap with a most significant bit of the adjacent and low-order block, and calculates a partial product of each of the blocks and the other input term based on Booth recoding in which a sign is controlled when Booth recoding values become ±0. The second processing circuitry simplifies the partial products. The adder circuitry outputs the sum of a result obtained through the simplification and an addition term. The saturation logic circuitry executes saturation processing based on a result outputted by the second processing circuitry and a result outputted by the adder circuitry.