Booth Recoding Multiplier for GPP DSP Hybrid Processing
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Solution Overview
Problem
Modern applications require processors that can seamlessly integrate general-purpose processing and digital signal processing capabilities, which existing processors fail to achieve effectively due to separate implementations of general-purpose processors (GPPs) and digital signal processors (DSPs.
Innovation Solution
The development of processor cores and multipliers that support both vector and single value multiplication, enabling fractional arithmetic, integer arithmetic, saturation, and SIMD operations by generating partial products and combining them to support various GPP and DSP operations through hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate implementations of GPPs and DSPs are used, then specialized processing capabilities are achieved, but device complexity and integration requirements increase
Solution Approach 1:
The patent combines GPP and DSP functionalities into a single processor core by integrating general-purpose execution units with specialized DSP instruction sets and hardware accelerators, eliminating the need for separate processor implementations while maintaining both processing capabilities
Solution Approach 2:
The processor core is designed with universal execution units that can dynamically switch between GPP and DSP operations through instruction decoding and control logic, allowing a single processor to perform multiple specialized functions without requiring separate dedicated hardware for each processing type
2Adaptability or versatility
If multiple instruction types are supported in a single processor, then versatility improves, but instruction precision and operational clarity may deteriorate
Solution Approach 1:
The instruction set is segmented into distinct GPP and DSP instruction categories with separate decoding paths and execution unit assignments, allowing the processor to precisely identify and execute the appropriate instruction type without confusion, even while supporting multiple operation types in a single core
3Device complexity
If GPP and DSP functionalities are consolidated into a single processor, then device integration improves, but processing speed may be compromised
Solution Approach 1:
The processor employs dynamic instruction dispatch and execution unit allocation that adapts in real-time based on the instruction type being executed, allowing the system to optimize processing speed for each operation by routing DSP-intensive tasks to specialized hardware accelerators and GPP tasks to general-purpose execution units within the same processor core
Data Source
AI summary
The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.