High Radix Booth Subset Code Multiplier for FPGA Area Reduction
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Solution Overview
Problem
Soft multipliers in modern FPGA architecture are inefficient due to high area, power, and routing resource consumption, making them unsuitable for machine learning applications.
Innovation Solution
Mapping high Booth radix 8 subset coding to a single level of FPGA logic reduces the size and power consumption of soft multipliers, improving their packing efficiency and routability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If soft multipliers are implemented using conventional memory-based architecture in modern FPGA, then the number of available multipliers increases, but area consumption, power consumption, and routing resource usage increase significantly
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional memory-based soft multiplier architecture to a high radix Booth subset coding architecture. This changes the fundamental operational parameters of the multiplier, enabling it to perform multiplication using shifted and added partial products with reduced resource requirements. The parameter change in architectural approach directly resolves the contradiction by achieving multiplier functionality with lower area consumption.
Solution Approach 2:
The patent extracts the essential multiplication function from the memory-based architecture and implements it using a dedicated high radix Booth subset coding unit. By taking out the core computational logic and separating it from general-purpose memory resources, the design achieves efficient multiplication without consuming significant FPGA memory bandwidth or area, thus resolving the contradiction between multiplier availability and area consumption.
2Adaptability or versatility
If soft multipliers are implemented using conventional memory-based architecture, then multiplier capacity increases, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters from memory-access-based multiplication to arithmetic logic-based multiplication using Booth subset coding. This parameter change eliminates the high power consumption associated with memory I/O operations while maintaining multiplier capacity, directly resolving the contradiction between multiplier capacity and power consumption.
3Adaptability or versatility
If soft multipliers are implemented using conventional memory-based architecture, then multiplier availability increases, but routing resource consumption increases
Solution Approach 1:
The patent extracts the multiplication logic from memory-based implementation and implements it using a self-contained high radix Booth subset coding unit with integrated routing. This extraction eliminates the need for extensive external routing resources while maintaining multiplier availability, resolving the contradiction between multiplier availability and routing resource consumption.
4Area of stationary object
If high Booth radix 8 subset coding is mapped to single level of FPGA logic, then area usage is reduced, but logic level complexity increases
Solution Approach 1:
The patent segments the multiplication operation into high radix Booth subset coding stages that can be mapped to single level FPGA logic. By dividing the complex multiplication task into manageable segmented stages with standardized coding, the design reduces overall area usage while keeping individual logic level complexity manageable through systematic segmentation.
Solution Approach 2:
The patent applies dimensionality change by mapping the high radix Booth subset coding to a single level of FPGA logic hierarchy. This dimensional reorganization consolidates multiple logic levels into one, reducing the vertical dimension of the circuit and thereby reducing area usage while managing complexity through horizontal expansion of the logic stage.
Data Source
AI summary
Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.