Semiconductor Device Bias Voltage Retention Using Bootstrap Circuit
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining bias voltage without degradation and extending the hold period of sampled bias voltage due to limitations in existing bootstrap circuits, particularly in sample-and-hold circuits, where voltage increase is hindered by increased element count and leakage currents.
Innovation Solution
A semiconductor device structure utilizing transistors with extremely low off-state current, specifically those with oxide semiconductor channels, and capacitive coupling to increase gate voltage, allowing for improved bias voltage retention and extended hold periods without increasing the number of elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional bootstrap circuit is used to increase gate voltage, then the bias voltage can be sampled, but the number of elements increases and leakage current causes the bias voltage to decrease over time
Solution Approach 1:
The patent combines the bootstrap circuit functionality with the sample-and-hold circuit by sharing the transistor M1 and capacitor C1 between both functions. This merging eliminates the need for separate dedicated bootstrap components, thereby reducing the total element count while maintaining voltage sampling capability.
Solution Approach 2:
The transistor M1 and capacitor C1 serve dual purposes: they function as the core sampling elements for the sample-and-hold circuit and simultaneously provide the bootstrap voltage boosting function. This multi-functionality allows a single element to fulfill multiple roles, reducing overall circuit complexity.
2Measurement precision
If a conventional bootstrap circuit is used to increase gate voltage, then the bias voltage can be sampled, but leakage current via transistor causes the bias voltage to decrease over time
Solution Approach 1:
The patent changes the operating parameters of the transistor by applying a boosted gate voltage through the bootstrap circuit. This parameter change (increased gate voltage) enhances the transistor's ability to maintain the hold capacitor voltage, thereby improving bias voltage stability during the hold period and reducing the effect of leakage current.
Solution Approach 2:
The bootstrap circuit dynamically adjusts the gate voltage of the switching transistor based on the power supply voltage. By continuously boosting the gate voltage to maintain an adequate voltage differential, the circuit adapts to changing conditions and maintains reliable bias voltage holding over extended periods.
3Productivity
If conventional transistors are used in the sample-and-hold circuit, then the circuit can operate, but leakage current prevents long-term bias voltage holding
Solution Approach 1:
The patent changes the voltage parameter applied to the transistor gate through the bootstrap circuit. By increasing the gate voltage above the power supply voltage, the transistor maintains a stronger electric field that reduces off-state leakage current, thereby extending the bias voltage hold period while maintaining operational performance.
Solution Approach 2:
The bootstrap circuit preemptively increases the gate voltage before the hold period begins, creating a conditions that minimize leakage current from the start. This preliminary action counteracts the inevitable leakage that would occur with conventional voltage levels, enabling long-term voltage holding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables semiconductor devices to maintain bias voltage without degradation and extend the hold period of sampled voltage, reducing power consumption by minimizing leakage currents and eliminating the need for continuous operation of bias generation circuits.
Implementation Method 1
A bootstrap circuit that generates a voltage higher than or equal to a power supply voltage using capacitive coupling is known
Data Source
AI summary
Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current.