Bootstrap Buffer Circuit for High-Linearity ADC Input Sampling
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Solution Overview
Problem
Traditional input buffers in analog-to-digital converters suffer from low linearity, high power consumption, and unconfigurable output signal bandwidth, which limits their performance in high-speed sampling applications.
Innovation Solution
A buffer circuit design that includes an input follower circuit, linearity boosting circuits, voltage bootstrap circuits, and compensation follower circuits to improve linearity without increasing current, while allowing adjustable output impedance and power consumption based on input signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bias current of the input buffer is increased to improve linearity, then the linearity improves, but the power consumption increases significantly
Solution Approach 1:
The patent changes the operating parameters by using variable bias current that adapts to input signal conditions, and employs voltage bootstrap techniques to modify the effective impedance seen by the sampling capacitor, thereby improving linearity without proportionally increasing power consumption
Solution Approach 2:
The patent introduces an input buffer as an intermediary circuit between the signal source and sampling capacitor. This buffer includes transistors configured with voltage bootstrap circuits that act as mediators to control the impedance dynamics, isolating the signal source from kickback effects while maintaining power efficiency
2Manufacturing precision
If the bias current is increased to reduce the impact of sampling capacitor current variations, then the follower nonlinearity decreases, but the power consumption increases
Solution Approach 1:
The patent employs dynamic biasing where the bias current and voltage are not fixed but vary with signal conditions. The voltage bootstrap circuits dynamically adjust the gate-source voltages of follower transistors to maintain optimal operating points across different signal levels, achieving consistent linearity without requiring maximum bias current throughout
Solution Approach 2:
The patent modifies key parameters including the effective transconductance and output impedance of follower stages through voltage bootstrap techniques. By changing these parameters dynamically based on signal amplitude and frequency, the circuit maintains high linearity across varying conditions without the penalty of continuously high power consumption
3Device complexity
If fixed device sizes are used in the buffer, then the circuit is simple, but the output impedance is not adjustable and bandwidth is limited
Solution Approach 1:
The patent introduces dynamic control mechanisms where the output impedance can be adjusted in response to different operating conditions. The voltage bootstrap circuits and biasing networks are configured to allow variable impedance presentation to the sampling network, enabling adaptation to different bandwidth requirements and signal conditions without changing the physical device sizes
Solution Approach 2:
The patent designs the buffer circuit to perform multiple functions: it provides voltage buffering, impedance transformation, linearity improvement, and adaptive output impedance control. The same core transistor structures serve multiple purposes through clever biasing and feedback arrangements, achieving versatility without proportionally increasing device count or complexity
Data Source
AI summary
The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.