Bootstrap Gate Switching Circuit for Linear SAR ADC Sampling
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Solution Overview
Problem
Existing sampling switch circuits in SAR ADCs suffer from non-linearity due to varying input voltages, leading to reduced digital signal accuracy and increased power consumption, especially in common mode voltage sampling structures.
Innovation Solution
A gate voltage bootstrap switching circuit using a low dropout regulator and MOS transistors with identical gate-source voltages, connected through a voltage control unit, to minimize impedance non-linearity and enhance conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional complementary switch structure is used, then charge injection is eliminated, but impedance non-linearity occurs due to different threshold voltages of N-type and P-type MOS transistors
Solution Approach 1:
The patent changes the gate voltage parameter from conventional fixed voltage to dynamically boosted voltage. By applying a gate voltage that is boosted by the bootstrap capacitor, the MOS transistor operates in a parameter regime where the enhanced gate-source voltage compensates for threshold voltage variations, maintaining consistent on-resistance across different input voltages and eliminating impedance non-linearity.
Solution Approach 2:
The patent uses a bootstrap capacitor to pre-charge or pre-boost the gate voltage before the MOS transistor switches. This preliminary action of storing energy in the bootstrap capacitor during the non-sampling phase ensures that when the transistor switches during sampling, the gate voltage is already at the optimal level to maintain linear impedance characteristics.
2Device complexity
If conventional switch structure is used, then circuit complexity is low, but conversion speed of ADC is limited due to higher MOS transistor impedance
Solution Approach 1:
The bootstrap capacitor is charged in advance during the non-sampling phase, storing the necessary energy to provide a boosted gate voltage during the sampling phase. This preliminary charging action ensures that when sampling occurs, the MOS transistor immediately has the enhanced gate voltage needed for low impedance and fast switching, improving ADC conversion speed without adding complex real-time control circuitry.
3Adaptability or versatility
If separate capacitor arrays are used for single-ended and differential modes, then mode versatility is achieved, but capacitance value and area increase leading to higher power consumption
Solution Approach 1:
The patent designs the capacitor array to serve multiple functions: it acts as both the sampling capacitor and the bootstrap capacitor for gate voltage generation. The same physical capacitors are reused in different configurations for single-ended and differential modes, eliminating the need for separate capacitor arrays and reducing overall capacitance requirements, area, and power consumption while maintaining mode versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit eliminates impedance non-linearity and reduces power consumption by providing consistent gate-source voltages to MOS transistors, improving the conversion speed and reducing capacitance requirements.
Implementation Method 1
A non-inverting input terminal of the LDO is connected to an external reference voltage, an inverting input terminal of the LDO is connected to an output terminal of the LDO which outputs a common mode voltage
Implementation Method 2
considering the non-linearity caused by charge injection, the switch S1 in FIG. 1 uses the transmission gate form switch (MOS switch)
Data Source
AI summary
A gate voltage bootstrap switching circuit includes an LDO, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a voltage control unit. The LDO has an inverting input terminal of connected to its output terminal. Drain of the first MOS transistor and source of the third MOS transistor are connected to the output terminal, source of the first MOS transistor is connected to drain of the second MOS transistor, and source of the second MOS transistor is connected to drain of the third MOS transistor. Capacitor arrays are connected. The voltage control unit is connected to gates of the first, second, and third MOS transistors to input an external power supply voltage as a gate-source voltage to the MOS transistors. The circuit eliminates the non-linearity of the impedance of the switch MOS transistors and improves the conversion speed of the ADC.