Bootstrap Circuit Node Splitting for Stable High-Speed Operation

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Solution Overview

Problem

Bootstrap circuits in shift register circuits face issues due to abrupt level changes caused by parasitic capacitors, leading to incorrect operations, especially at higher operating speeds.

Innovation Solution

The implementation of a bootstrap circuit configuration that includes specific connections between transistors and capacitors, such as a voltage-variation repression capacitor between the node section and the first voltage supply line, and the use of additional transistors to split the node section, reducing the impact of abrupt level changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operating speed of the bootstrap circuit is increased, then the productivity is improved, but the reliability deteriorates due to incorrect operations caused by abrupt level changes from parasitic capacitors

Engineering Contradiction:
Improveoperating speedVSAvoidoperation correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A node section is introduced as an intermediary between the first transistor and the third transistor. This node section acts as a buffer that isolates the direct connection, thereby reducing the impact of abrupt level changes from parasitic capacitors on the bootstrap circuit's operation correctness while maintaining high operating speed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate electrode of the first transistor is extracted from the direct connection to the third transistor's source/drain area and instead connected to the node section. This extraction removes the harmful direct coupling that causes abrupt level changes to affect operation correctness, allowing the circuit to operate reliably at higher speeds

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the number of transistors is increased to split the node section, then the reliability is improved by reducing abrupt level changes, but the device complexity increases

Engineering Contradiction:
Improveoperation stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The node section is segmented into multiple portions by introducing additional transistors (fourth and fifth transistors) that divide the node section. This segmentation reduces the capacitance of each individual node portion, thereby reducing abrupt level changes and improving operation stability while adding only a limited number of circuit elements

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces the effects of abrupt level changes, stabilizing the operation of the bootstrap circuit and preventing incorrect operations, even at higher speeds.

Implementation Method 1

a voltage-variation repression capacitor wired between the node section and the first voltage supply line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a bootstrap capacitor Ca wired between the gate electrode of the first transistor Tr1 and the specific one of the source/drain areas of the first transistor Tr1

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8040163B2Bootstrap circuit
Publication Date: 2011.10.18 SONY GROUP CORP
  • US8040163B2 patent drawing
  • US8040163B2 patent drawing
  • US8040163B2 patent drawing

AI summary

Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.