Master Bootstrap Processor Register Communication
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Solution Overview
Problem
The existing method of using an advanced programmable interrupt controller (APIC) for inter-processor communication during the boot process of data processing devices is slow due to the need for broadcasting remote read interrupts and waiting for acknowledgement from each slave processor.
Innovation Solution
The use of PCI registers and model-specific registers (MSRs) allows for faster inter-processor communication by writing configuration information directly to slave processors' registers and using acknowledgment values within the PCI bus protocol, bypassing the need for APIC-based broadcasts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If APIC-based remote read IPI is used for inter-processor communication, then configuration information can be transmitted to slave processors, but the communication speed is slow due to broadcasting and waiting for acknowledgement from each slave processor
Solution Approach 1:
The patent extracts the configuration communication function from the APIC-based interrupt mechanism and implements it through direct PCI register writes. By removing the broadcast-acknowledge sequence and using direct register access, the system achieves faster communication speed while reducing the time lost in waiting for slave processor acknowledgements during the boot process.
2Productivity
If master bootstrap processor broadcasts remote read IPI to all processors, then configuration information can be delivered to slave processors, but the process becomes complex and time-consuming
Solution Approach 1:
The patent simplifies the communication protocol by extracting the essential configuration delivery function from the complex APIC broadcast mechanism. Direct PCI register writes eliminate the need for interrupt broadcasting and acknowledgement waiting, thereby improving boot process efficiency while reducing protocol complexity.
Solution Approach 2:
The patent uses PCI registers as an intermediary mechanism for configuration communication between master and slave processors. This intermediary approach replaces the complex APIC-based interrupt system with a simpler direct register access mechanism, facilitating faster and more efficient configuration information transfer during boot.
3Speed
If sequential memory-mapped reads and writes are performed for remote read, then configuration information can be transmitted, but the operation speed is reduced
Solution Approach 1:
The patent extracts the configuration communication function from the sequential memory-mapped read/write operations and implements it through direct PCI register writes. This extraction eliminates the sequential operation bottleneck and achieves faster data transfer speed by reducing the time required for configuration information communication between processors.
Data Source
AI summary
During a boot process of a data processing device having a master bootstrap processor device and multiple slave processor devices, memory associated with the master bootstrap processor is not accessible. Accordingly, the master bootstrap processor communicates configuration information to a slave processor by writing configuration information to a register associated with the slave processor. The slave processor communicates an acknowledgment to the master bootstrap processor in response to reading the configuration information.