Bootstrap Sample-and-Hold Circuit for ADC Channel Bandwidth Matching
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Solution Overview
Problem
Existing sampling switch circuits face challenges in precisely controlling frequency bandwidth, gain, and phase, especially in multi-channel systems with time-interleaved ADCs, where bandwidth mismatches lead to reduced spurious-free dynamic range and increased power consumption in high-data-rate applications.
Innovation Solution
The proposed solution involves a sample and hold circuit with a signal bootstrap circuit generating a control voltage based on a clock signal to control the sampling switch transistor, and a static bootstrap circuit generating a programmable control voltage to control common mode switch transistors, allowing for precise control of performance properties like frequency bandwidth, gain, and phase across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If voltage mode sampling with simple switch transistors is used, then circuit complexity is reduced, but bandwidth control precision and performance matching between channels deteriorate
Solution Approach 1:
The patent applies parameter changes by introducing programmable control voltages that can dynamically adjust the on-resistance of switch transistors. The control circuitry modifies the gate-source voltage parameters of the switches to precisely control bandwidth, gain, and phase characteristics, enabling accurate performance matching between multiple channels while maintaining manageable circuit complexity through systematic parameter adjustment.
Solution Approach 2:
The patent implements dynamics by using clock-controlled circuitry that dynamically adjusts the control voltages applied to switch transistors during different phases of the sampling process. This dynamic control allows the circuit to optimize its performance characteristics in real-time, improving bandwidth control precision without requiring permanently complex circuit architectures.
2Measurement precision
If higher control voltage magnitudes are applied to improve bandwidth matching, then bandwidth control precision is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by using control circuitry that adjusts control voltages only to the extent necessary to achieve the required bandwidth matching precision. Rather than applying maximum control voltage continuously, the circuit applies just sufficient voltage to correct bandwidth mismatches, thereby reducing unnecessary power consumption while maintaining adequate control precision.
Solution Approach 2:
The patent optimizes the balance between control precision and power consumption by dynamically adjusting control voltage parameters. The control circuitry monitors performance and modifies voltage magnitudes to achieve the minimum necessary control for bandwidth matching, avoiding excessive power dissipation while maintaining sufficient control precision for accurate bandwidth matching between channels.
3Use of energy by moving object
If simple voltage mode sampling is used, then power consumption is reduced, but performance property matching between channels deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where control circuitry monitors the performance properties of multiple channels and dynamically adjusts control voltages to correct mismatches. This feedback control enables accurate performance property matching between channels while using power-efficient voltage mode sampling, as the system only consumes additional power when and where needed to correct specific mismatches rather than continuously operating at high power levels.
Solution Approach 2:
The patent achieves multi-functionality by using a single control circuitry that can adjust multiple performance properties (bandwidth, gain, phase) across multiple channels through programmable control voltages. This universal control approach maintains power efficiency while improving performance matching, as the same control infrastructure serves multiple functions rather than requiring separate high-power circuits for each performance parameter.
4Reliability
If clock-controlled circuitry with programmable control voltages is added, then bandwidth matching between channels is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the control function into modular components: clock-controlled circuitry that generates base control signals, programmable voltage sources that create control voltage magnitudes, and control circuitry that combines these to drive individual switch transistors in each channel. This segmented architecture improves bandwidth matching through precise control while managing complexity through functional decomposition and reuse of control modules across channels.
Data Source
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AI summary
A sample and hold circuit comprising: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.