Bootstrap Shift Register Leakage Current Control
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Solution Overview
Problem
Existing display device driving circuits, particularly those using two-phase, three-phase, or four-phase clock shift registers, are prone to malfunctions due to large leakage currents in transistors, leading to circuit failures and increased production costs.
Innovation Solution
A bootstrap circuit that generates an output signal using a first transistor and control means, where the first transistor is rendered conductive by an input signal and non-conductive by a phase-shifted clock signal, preventing simultaneous conductive and non-conductive voltage states and reducing the need for external reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-phase clock shift register is used to reduce manufacturing complexity, then the number of process steps is reduced, but the circuit becomes vulnerable to malfunctions due to large leakage currents
Solution Approach 1:
The patent applies preliminary action by introducing a third clock phase that proactively resets the bootstrap capacitor before leakage currents can cause malfunction. This preventive reset action occurs in advance of potential failure conditions, clearing accumulated charge that would otherwise lead to circuit errors due to transistor leakage.
Solution Approach 2:
The patent implements periodic action by using a three-phase clock system where the third phase periodically resets the bootstrap capacitor at regular intervals. This periodic reset mechanism ensures that charge accumulation from leakage currents is continuously cleared, maintaining circuit reliability through repeated corrective action.
2Device complexity
If a two-phase clock shift register is used to simplify the circuit, then external reset signals are eliminated for most stages, but the last stage still requires a dedicated external reset signal
Solution Approach 1:
The patent applies universality by making the third clock phase serve multiple functions: it acts as a clock signal for timing operations and simultaneously serves as a reset signal for the bootstrap capacitor. This multi-functionality eliminates the need for separate dedicated reset signals, including for the last stage, as the third phase universally resets all stages throughout the shift register chain.
Solution Approach 2:
The patent merges the reset function into the clock signal system by combining the bootstrap capacitor reset operation with the third phase of the clock signal. This consolidation integrates what would otherwise be separate reset signal requirements into the existing clocking infrastructure, eliminating the need for additional external reset signals.
3Ease of manufacture
If transistors of single conductivity type are used to reduce manufacturing complexity, then both n-channel and p-channel transistor fabrication is avoided, but the driving circuit requires more complex clock signal phases
Solution Approach 1:
The patent applies parameter changes by modifying the temporal characteristics of the clock signals, introducing a three-phase timing system with specific phase relationships. This change in the time-domain parameters of the clock signals enables the single-conductivity-type transistor circuit to properly control the bootstrap capacitor charging and discharging cycles, compensating for the simplified transistor fabrication with more sophisticated timing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents circuit malfunctions even with high leakage currents and reduces the complexity and cost of the driving circuit by eliminating the need for additional reset signals, improving the operational reliability of display devices.
Implementation Method 1
Each shift register stage is formed by a circuit exploiting a bootstrap effect
Data Source
AI summary
Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.