Distributed Bootstrap Switch Layout for Signal-Independent ADC Sampling
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Solution Overview
Problem
Existing bootstrapping techniques for Metal-Oxide-Semiconductor (MOS) switches in high-speed pipeline analog-to-digital converters face challenges in achieving efficient and accurate signal sampling due to signal-dependent parasitic capacitance and delays, especially at clock rates exceeding 300 MHz, leading to premature overload and distortion.
Innovation Solution
A distributed bootstrapping approach with a circuit design that includes multiple switches to efficiently connect a capacitor to both terminals of a sampling network, allowing for a constant gate-source voltage independent of the input signal, reducing parasitic capacitance and enabling faster switching and more accurate sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional bootstrapping techniques are used in high-speed pipeline ADCs, then the gate voltage can be enhanced to improve switch linearity, but signal-dependent parasitic capacitance and delays increase, leading to premature overload and distortion at clock rates exceeding 300 MHz
Solution Approach 1:
The bootstrapping circuit is segmented into multiple independent switches (first switch, second switch, third switch, fourth switch, fifth switch) that separately control different connections. This segmentation allows each switch to be optimized for specific functions, reducing overall parasitic effects and enabling better control over signal-dependent capacitance and delays in high-speed ADC applications
Solution Approach 2:
A capacitor is introduced as an intermediary element between the switches and the sampling network. This capacitor acts as a mediator that stores and transfers charge, enabling the bootstrapping effect to maintain constant gate-source voltage while reducing signal-dependent parasitic effects. The capacitor serves as a buffer that decouples the direct signal path from the control voltage path, thereby reducing distortion at high clock rates
2Measurement precision
If the sampling time is increased to eliminate residual transient effects and improve signal tracking accuracy, then the sampling precision is improved, but the device complexity and circuit design difficulty increase
Solution Approach 1:
The bootstrapping circuit performs preliminary action by pre-charging the capacitor and establishing the gate-source voltage before the actual sampling operation. The switches are configured to prepare the circuit state in advance, ensuring that transient effects are minimized and the sampling network is ready for accurate signal tracking from the outset, thereby improving precision without requiring excessively long sampling times
Solution Approach 2:
The circuit employs periodic switching action with multiple switches operating in coordinated phases. This periodic action allows the bootstrapping circuit to refresh and maintain the gate-source voltage at regular intervals, ensuring continuous accurate signal tracking while managing complexity through rhythmic, predictable switching patterns that can be synchronized with the ADC clock
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides signal-independent loading, matched sampling, and maximum sampling time, reducing signal-dependent delays and distortion, thereby enhancing the precision and accuracy of analog signal sampling in high-speed ADCs.
Implementation Method 1
a first switch for connecting electrical power to a first terminal of a capacitor; a second switch for connecting a second terminal of the capacitor to a signal to be sampled
Data Source
AI summary
An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.