Bootstrap Capacitor Voltage Clamping for Half-Bridge Gate Drivers

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Solution Overview

Problem

Half-bridge switching stages using n-channel FETs face challenges in maintaining the power supply voltage for upper driver circuitry within a specified range due to variations caused by lower FET on-resistance and current sense resistor resistance, which can lead to excessive gate-to-source voltage, potentially damaging the FETs.

Innovation Solution

Incorporation of charging control circuitry to regulate the charging of the boot-strap capacitor and clamping circuitry to limit the power supply voltage within permissible limits, using a comparator and discharge transistor to maintain the voltage within a predetermined range, along with soft-start circuitry to manage start-up conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a boot-strap capacitor is used to power upper driver circuitry, then the driver circuitry can be powered, but the power supply voltage varies due to lower FET on-resistance and current sense resistor resistance

Engineering Contradiction:
Improvedriver circuitry power supply stabilityVSAvoidpower supply voltage range
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by proactively regulating the boot-strap capacitor charging voltage through a voltage regulator circuit before the voltage variations can cause damage. The regulator pre-establishes a stable voltage reference and actively controls the charging process to prevent excessive voltage buildup, rather than waiting for voltage to exceed safe limits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through a voltage regulator circuit that continuously monitors the boot-strap capacitor voltage and adjusts the charging current accordingly. The regulator uses feedback from the actual voltage level to maintain it within the specified range, compensating for variations caused by lower FET on-resistance and current sense resistor resistance.

Inventive Principle:
Principle #23Feedback

2Device complexity

If the power supply voltage for upper driver circuitry is not regulated, then the circuit is simpler, but excessive gate-to-source voltage can damage the FETs

Engineering Contradiction:
Improvepower supply regulation circuitVSAvoidexcessive gate-to-source voltage
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary voltage regulator circuit between the power supply and the upper driver circuitry. This intermediary component buffers and conditions the power, isolating the sensitive FET gates from voltage spikes and variations. The regulator acts as a mediator that transforms unregulated voltage into a controlled, safe voltage level.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies beforehand cushioning by providing a voltage regulator that prevents excessive voltage from reaching the driver circuitry in the first place. The regulator circuit is designed to clamp or limit the voltage before it can exceed safe thresholds, cushioning the protective effect against potential damage before it occurs.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively stabilizes the power supply voltage for upper driver circuitry, preventing damage to FETs by ensuring it remains within the specified range, even under varying load conditions and during start-up, thereby enhancing the reliability and safety of the half-bridge switching stage.

Implementation Method 1

a boot-strap capacitor electrically coupled between a switching node and the upper driver circuitry and configured to power the upper driver circuitry

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

variations caused by lower FET on-resistance and current sense resistor resistance

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12597856B2Systems and methods for powering driver circuitry
Publication Date: 2026.04.07 MAXIM INTEGRATED PROD INC
  • US12597856B2 patent drawing
  • US12597856B2 patent drawing
  • US12597856B2 patent drawing

AI summary

A method for powering driver circuitry for an upper transistor of a half-bridge switching stage includes (1) selectively charging a boot-strap capacitor via a first voltage source such that a voltage at the boot-strap capacitor remains within a predetermined voltage range, (2) clamping the voltage at the boot-strap capacitor to prevent the voltage at the boot-strap capacitor from exceeding a predetermined maximum value, and (3) electrically powering the driver circuitry at least partially via the boot-strap capacitor.