Bootstrapped Input Buffer for Gigahertz ADC Sampling
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Solution Overview
Problem
Designing high-speed analog-to-digital converters (ADCs) that can efficiently handle high-frequency input signals in the gigahertz range poses challenges due to the need for fast and accurate conversion while maintaining performance specifications such as signal-to-noise-and-distortion ratio (SINAD) and spurious free dynamic range (SFDR, especially in applications requiring wide bandwidth and low cost.
Innovation Solution
The implementation of a bootstrapped switching circuit with a jump start circuit to accelerate the turn-on time of the sampling switch, utilizing a positive feedback loop and a bootstrapped gate voltage generator to ensure quick transistor activation, and an input buffer with a push-pull architecture and level shifters to minimize distortion and optimize voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional switching circuit is used in high-speed ADCs, then the circuit complexity is low, but the sampling speed is insufficient for gigahertz-range signals
Solution Approach 1:
The jump start circuit activates the output transistor before the positive feedback loop completes, preparing the bootstrapped gate voltage generator to quickly establish the required gate voltage when sampling begins. This preliminary action reduces the turn-on time of the sampling switch, enabling gigahertz-range sampling speeds.
Solution Approach 2:
The positive feedback loop uses the output voltage to reinforce the gate voltage of the sampling switch through the bootstrapped gate voltage generator. This feedback mechanism ensures rapid and complete turn-on of the sampling switch, achieving fast sampling speeds while maintaining circuit simplicity.
2Measurement precision
If the turn-on time of the sampling switch is extended to improve switching completeness, then the sampling accuracy improves, but the sampling speed decreases
Solution Approach 1:
The jump start circuit pre-activates the output transistor to prepare the bootstrapped gate voltage generator, enabling the gate voltage to reach its target level faster. This preliminary action achieves both complete switching and fast turn-on, resolving the trade-off between sampling accuracy and speed.
Solution Approach 2:
The bootstrapped gate voltage generator dynamically adjusts the gate voltage parameter using positive feedback, ensuring the sampling switch achieves complete turn-on with minimal time. This parameter control mechanism simultaneously improves switching completeness and reduces turn-on time.
3Reliability
If a simple buffer architecture is used, then the device complexity is low, but the voltage level matching and distortion performance are insufficient
Solution Approach 1:
The bootstrapped gate voltage generator uses positive feedback to dynamically adjust the gate voltage, ensuring accurate voltage level matching between stages. This feedback mechanism improves signal fidelity by minimizing distortion while maintaining a relatively simple buffer architecture.
Solution Approach 2:
The level shifter circuit transforms the voltage parameter from the input range to the optimal range for the subsequent stage. This parameter transformation ensures proper voltage level matching and reduces distortion without requiring complex buffer architecture.
Data Source
AI summary
The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.