Bootstrapped Cascode Voltage Translator for Faster HV Switching
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Solution Overview
Problem
Traditional voltage level translators face challenges in achieving high-speed voltage translation due to large high-voltage devices with high input and output capacitance, leading to slow speed and timing variability, and require continuous DC current bias paths, which limits their efficiency and speed.
Innovation Solution
The implementation of an automatically bootstrapped cascode driver that combines a high-voltage and low-voltage switch in a cascode arrangement, where the high-voltage switch is dynamically bootstrapped from the same logic level signal driving the low-voltage switch, reducing parasitic and gate capacitances, and eliminating DC current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional high-voltage devices are used for voltage level translation, then voltage translation function is achieved, but speed is reduced due to high input and output capacitance
Solution Approach 1:
The patent divides the single high-voltage switch into a cascode structure with multiple transistors (HV NFET, LV NFET, and PFETs), segmenting the voltage translation function across multiple smaller devices with lower individual capacitances, thereby achieving faster switching speeds while maintaining the voltage translation capability
Solution Approach 2:
The patent implements dynamic bootstrapping of the HV NFET gate voltage during switching transitions, dynamically adjusting the gate drive voltage to optimize switching speed. This dynamic control reduces the effective capacitance impact by providing enhanced drive strength during transitions rather than relying on static high-voltage devices with inherently high capacitance
2Use of energy by moving object
If traditional voltage level translators are used, then voltage domain isolation is achieved, but continuous DC current consumption occurs
Solution Approach 1:
The patent replaces continuous DC bias paths with periodic switching action. The voltage translation is achieved through controlled switching transitions of the cascode transistor network, which operates in discrete on/off states rather than continuous conduction, thereby eliminating steady-state DC current consumption while maintaining isolation between voltage domains
Solution Approach 2:
The bootstrapped gate voltage for the HV NFET is generated automatically from the input signal itself through the capacitor coupling mechanism, eliminating the need for external continuous bias current sources. The circuit uses its own operating signals to maintain optimal switching conditions without requiring additional power consumption
3Measurement precision
If high-voltage devices are used for precise analog operation, then signal to noise ratio is improved, but area and cost increase
Solution Approach 1:
The patent applies high-voltage operation selectively only where needed for precise analog operation (in the HV NFET and associated high-voltage circuitry), while using low-voltage devices for logic functions. This localized application of high-voltage operation maintains the signal-to-noise ratio benefits only in the critical analog path without requiring all circuit elements to be large high-voltage devices, thereby reducing overall area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces overall delay and timing variability, improving DC/DC conversion efficiency and reducing charge consumption and supply noise during switching events, while enhancing the loop response of control systems by minimizing phase delay.
Implementation Method 1
a capacitor connected between the LV gate and the HV gate. The capacitor is configured to bootstrap the intermediate voltage to a bootstrapped voltage in response to a positive voltage transition of the voltage pulse
Data Source
AI summary
A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.