Bootstrapped Gain Enhancement Circuit for Low-Noise Pixel Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solid-state image sensors in camera systems suffer from low conversion gain, photo response nonuniformity, and fixed pattern noise due to mismatches in capacitance, which are exacerbated by circuitry additions intended to increase gain, leading to increased noise and reduced bandwidth.
Innovation Solution
A gain enhancement circuit that dynamically couples and decouples the gate-to-source capacitance of a reset transistor across an operational amplifier, reducing effective capacitance and thereby increasing conversion gain while minimizing noise and bandwidth reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuitry is added to increase conversion gain, then conversion gain is improved, but noise increases and bandwidth is reduced
Solution Approach 1:
The patent applies bootstrapping technique to dynamically control the reset transistor gate voltage, making the capacitance value time-dependent. During the reset phase, the gate is pulled to a higher voltage to increase gate-to-source capacitance for better reset accuracy. During the signal readout phase, the gate voltage is adjusted to optimize the conversion gain without adding noise-sensitive circuitry.
Solution Approach 2:
The invention changes the operating voltage parameters of the reset transistor dynamically. By applying different voltages to the gate during different phases (reset vs. readout), the effective capacitance values are optimized for each phase, achieving high conversion gain during readout while maintaining proper reset function, without requiring additional noisy circuitry.
2Measurement precision
If circuitry is added to increase conversion gain, then conversion gain is improved, but bandwidth is reduced
Solution Approach 1:
The bootstrapped circuit dynamically adjusts the gate voltage timing to optimize both gain and bandwidth. The controlled timing of gate voltage transitions ensures that capacitance modulation occurs during phases that do not conflict with the signal bandwidth requirements, maintaining fast response while achieving gain enhancement.
Solution Approach 2:
The circuit employs periodic voltage transitions to the reset transistor gate, synchronized with the pixel readout cycle. This periodic bootstrapping action enhances conversion gain during the integration and readout phases without introducing continuous disturbances that would reduce bandwidth, as the voltage transitions are timed to coincide with natural signal cycle boundaries.
3Manufacturing precision
If capacitance matching is improved to reduce PRNU and FPN, then image quality is improved, but device complexity increases
Solution Approach 1:
The bootstrapped reset transistor circuit performs self-adjustment of its gate voltage based on the signal phase, automatically optimizing its capacitance characteristics without requiring external calibration circuitry or additional matching components. The circuit serves itself by using the signal timing to control the gate voltage, achieving improved capacitance matching while avoiding additional complexity.
Data Source
AI summary
In accordance with an embodiment, a gain enhancement circuit includes an amplifier having an input terminal, a transistor coupled to the input terminal and a capacitance dynamically coupled to another input terminal of the amplifier by a switch, wherein the capacitance is a parasitic element of the transistor.