Bootstrapped Sample-and-Hold Circuit for ADC Bandwidth Matching
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Solution Overview
Problem
Existing sampling switch circuits and sampling circuitry face challenges in precisely controlling frequency bandwidth, gain, and phase, especially in high-bandwidth applications, leading to inaccuracies in digital output signals and limitations in time-interleaved ADC systems.
Innovation Solution
A sample and hold circuit with a signal bootstrap circuit and a static bootstrap circuit to generate control voltages that precisely control the on-resistance of sampling switch transistors, allowing for precise control of performance properties such as frequency bandwidth, gain, and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage mode sampling is used with simple switch transistors, then the circuit complexity is low, but the control precision of frequency bandwidth, gain, and phase is insufficient
Solution Approach 1:
The patent applies parameter changes by controlling the gate-source voltage of the sampling switch transistor to precisely adjust its on-resistance. By varying the control voltage applied to the gate terminal, the on-resistance can be tuned to achieve precise control of frequency bandwidth, gain, and phase characteristics, resolving the contradiction between simple circuit structure and precise performance control.
Solution Approach 2:
The patent implements feedback mechanisms through bootstrap circuits that sense the input voltage level and dynamically adjust the gate control voltage accordingly. This feedback loop ensures that the sampling switch maintains precise on-resistance control across varying signal conditions, achieving accurate frequency bandwidth and gain control without requiring complex external circuitry.
2Manufacturing precision
If simple sampling switch circuits are used, then the ease of manufacture is high, but the matching precision between multiple channels is poor
Solution Approach 1:
The patent employs universal bootstrap circuit designs that can be replicated across multiple channels with identical architecture. Each channel uses the same control mechanism and circuit topology, ensuring consistent performance characteristics. This multi-functional approach allows precise matching between channels while maintaining ease of manufacture through standardized design replication.
3Object-generated harmful factors
If conventional sampling circuits are used in time-interleaved ADC systems, then the device complexity is low, but the time-interleaved frequency spurs are significant
Solution Approach 1:
The patent replaces conventional mechanical or simple electronic switching mechanisms with electrically controlled sampling switches whose on-resistance is precisely regulated by bootstrap circuits. This substitution enables dynamic control of sampling characteristics, reducing time-interleaved frequency spurs through precise impedance matching and timing control without requiring complex mechanical adjustment mechanisms.
Data Source
AI summary
A sample-and-hold circuit includes a sampling capacitor, a bootstrapped signal sampling switch transistor between an input voltage and a first node of the sampling capacitor, and a common-mode switch transistor connected between a second node of the sampling capacitor and a common-mode voltage. The bootstrapped signal sampling switch transistor is controlled by a gate voltage that is dependent on the input signal voltage so as to provide a substantially signal-independent gate-source voltage to turn on the transistor. The common-mode switch transistor is controlled by a programmable gate voltage such that it becomes possible to trim the series on-resistance of the above-mentioned switch transistors to allow for calibration of a sample-and-hold circuit bandwidth.