Bootstrapped Switch Gate Drive for Faster Clock Response
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Solution Overview
Problem
Conventional bootstrapped switches face limitations in rapid switching due to the design of the gate driver circuit, which affects their speed and accuracy in responding to system clocks.
Innovation Solution
The introduction of an inverter circuit and a second capacitor enhances the switching speed by rapidly pulling up or pulling down the voltage at a node, improving the transition speed of the control terminal of the transistor, thereby enabling faster turn-on and turn-off operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional gate driver circuit is used to control the NMOS transistor, then the circuit structure is simple, but the switching speed is limited and response time is slow
Solution Approach 1:
The gate driver circuit is designed with dynamic switching capability using multiple transistors (Q1-Q4) that can rapidly change the gate voltage state. The circuit transitions between different conduction states to achieve fast turn-on and turn-off of the NMOS transistor, making the gate driver itself dynamically responsive rather than static.
Solution Approach 2:
The patent introduces intermediate transistors (Q1, Q2, Q3, Q4) as mediator components between the control signal and the NMOS transistor gate. These intermediary transistors amplify and accelerate the voltage transition at the gate, acting as a buffer stage that speeds up the switching action without directly connecting the control signal to the NMOS gate.
2Loss of time
If the gate voltage transitions slowly, then the circuit is stable, but the response time to system clock is delayed and sampling accuracy decreases
Solution Approach 1:
The gate driver circuit performs preliminary voltage buildup action through the bootstrap capacitor and intermediate transistors before the NMOS transistor needs to switch. The circuit prepares the gate voltage in advance during the off-state, so when switching is required, the voltage is already ready to be applied rapidly, reducing the overall response time to the system clock.
Solution Approach 2:
The patent changes the voltage parameter at the NMOS gate by using a bootstrap mechanism that generates a voltage higher than the supply voltage. This parameter change (voltage boosting) allows the NMOS transistor to switch more rapidly and accurately, improving both response time and sampling accuracy by altering the electrical parameters of the gate drive.
3Productivity
If the voltage transition at the control terminal is slow, then power consumption is low, but the switching speed and operational performance are reduced
Solution Approach 1:
The gate driver circuit operates in periodic cycles, switching between charging and discharging states of the bootstrap capacitor. During each cycle, the intermediate transistors are activated only when needed to charge or discharge the capacitor, providing rapid voltage transitions periodically rather than continuously, which maintains high switching speed while managing power consumption through intermittent operation.
Data Source
AI summary
A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control terminal of the first transistor and the node. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the node and the output terminal of the inverter circuit.