Bootstrapped Switch Timing to Preserve Linearity

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Solution Overview

Problem

Bootstrapped switches with transistors face linearity issues due to parasitic capacitors causing unwanted discharge of the bootstrap capacitor, leading to a drop in linearity.

Innovation Solution

The design includes a bootstrapped switch configuration with specific transistor and switch arrangements, where the capacitor is charged in one clock phase and the control terminals are made equipotential in another, with a target switch turning on in a preset time interval to prevent parasitic capacitor charging, thereby maintaining linearity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transistors are used to implement switches in the bootstrapped switch, then the switch functionality is achieved, but parasitic capacitors of the transistors cause unwanted discharge of the bootstrap capacitor, resulting in a drop in linearity

Engineering Contradiction:
ImprovelinearityVSAvoidparasitic capacitor discharge
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by introducing a target switch that turns on in advance (in a preset time interval before the first clock phase ends or after the second clock phase starts) to proactively discharge parasitic capacitors before they can cause unwanted discharge of the bootstrap capacitor. This preemptive discharge action prevents the linearity degradation that would otherwise occur during normal operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The target switch acts as an intermediary component specifically designed to manage the parasitic capacitors. By providing a controlled discharge path through this intermediate element, the patent isolates the harmful effect of parasitic capacitor discharge from the bootstrap capacitor, thereby protecting the linearity of the bootstrapped switch while maintaining switch functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the bootstrap capacitor is charged during the first clock phase, then the switch can operate with high linearity, but the parasitic capacitors accumulate charge that causes discharge during subsequent operations

Engineering Contradiction:
ImprovelinearityVSAvoidbootstrap capacitor discharge
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies discarding and recovering by providing a dedicated path (through the target switch) to discard the accumulated charge in parasitic capacitors at appropriate times. The target switch enables selective discharge of parasitic capacitor charges that would otherwise be lost or cause harmful effects, thereby recovering the bootstrap capacitor's charge and maintaining system efficiency and linearity.

Inventive Principle:
Principle #34Discarding and recovering

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration diminishes the influence of parasitic capacitors, resulting in higher linearity compared to traditional bootstrapped switches by ensuring the control terminal voltage remains constant and equal to the sum of the input voltage and bootstrap capacitor voltage.

Implementation Method 1

a capacitor, a second transistor... The capacitor has a third terminal and a fourth terminal... The capacitor is charged in a first clock phase

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11070207B2Bootstrapped switch
Publication Date: 2021.07.20 REALTEK SEMICON CORP
  • US11070207B2 patent drawing
  • US11070207B2 patent drawing
  • US11070207B2 patent drawing

AI summary

A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. A first terminal of the second transistor receives the input voltage, and a second terminal of the second transistor is coupled to a first terminal of the capacitor. In a first clock phase, the capacitor is being charged. In a second clock phase, the control terminal of the first transistor and the control terminal of the second transistor are substantially equipotential with a second terminal of the capacitor. The control terminal of the first transistor and the control terminal of the second transistor are coupled to the power supply voltage within a predetermined time before the terminal of the first clock phase or within a predetermined time after the start of the second clock phase.