Border Circuit Layout Using Through-Substrate Interconnects
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Solution Overview
Problem
Existing electronic devices face challenges in achieving a compact, thin, and lightweight design due to suboptimal circuit arrangements in the border regions, which hinder the formation of a narrow border region.
Innovation Solution
The electronic device incorporates a substrate with a through hole, a connecting element, a first insulating layer with a via, and conductive elements arranged to prevent overlap with the connecting element, utilizing a semiconductor layer and conductive layers to ensure electrical connectivity while minimizing Cu diffusion and enhancing adhesion for a narrow border design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional circuit arrangement is used in the border region, then the device can be manufactured with standard processes, but the border region cannot be narrowed
Solution Approach 1:
The patent transitions from planar circuit arrangement to three-dimensional stacked arrangement. Conductive elements are positioned at different vertical levels (first conductive element above the substrate, second conductive element below the substrate), allowing circuits to route around the connecting element in the vertical dimension rather than competing for horizontal space, thus narrowing the border region while maintaining manufacturability
Solution Approach 2:
The patent implements nested positioning where the first conductive element is disposed above the substrate in a region that overlaps with the connecting element's projection, and the second conductive element is disposed below the substrate in a corresponding overlapping region. This nesting approach allows multiple conductive elements to occupy different vertical levels within the same horizontal footprint, reducing border width without increasing manufacturing complexity
2Reliability
If conductive elements are positioned to prevent overlap with connecting element, then Cu diffusion is reduced, but electrical connectivity becomes more complex
Solution Approach 1:
The patent segments the electrical connection path into distinct portions: the first conductive element connects to the connecting element from above, the second conductive element connects from below, and they are separated by a gap. This segmentation prevents Cu diffusion by ensuring no direct contact between copper-containing elements, while the connection complexity is managed through standardized via and conductive layer formation processes
3Strength
If multiple insulating layers are used to separate conductive elements, then adhesion is enhanced, but manufacturing steps increase
Solution Approach 1:
The patent specifies that the first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant that is different from the first. This parameter change allows optimization of adhesion properties at different interfaces while managing manufacturing complexity through selective material deposition processes that can be integrated into existing semiconductor fabrication workflows
Data Source
AI summary
An electronic device includes: a substrate including a through hole; a connecting element disposed in the through hole; a first insulating layer disposed on the substrate and including a first via; a first conductive element disposed on the first insulating layer and electrically connected to the connecting element through the first via; a second conductive element and a third conductive element disposed on the first conductive element and separated from each other by a space; a second insulating layer disposed in the space; a fourth conductive element disposed under the substrate and electrically connected to the connecting element; and a semiconductor disposed between the substrate and the first insulating layer, wherein, in a cross-sectional view of the electronic device, at least one of the second conductive element and the third conductive element is not overlapping with the connecting element.


