Borderless Contact Integration in Replacement Metal Gate Transistors
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Solution Overview
Problem
Integrating borderless contacts into the gate-last replacement metal gate (GL-RMG) process is challenging due to the compromise of top spacers during polishing and the need to recess work function metal and the metal gate to avoid contact with borderless contacts, which complicates the process and affects the integrity of the transistor structure.
Innovation Solution
A method involving a sacrificial gate structure with a dielectric layer, where a work-function layer is deposited and a gate conductor is formed, with spacers and selective etching used to isolate the work-function layer, allowing for the formation of borderless contacts without compromising the gate conductor or spacers, and subsequent dielectric material deposition to insulate the gate conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a non-RMG approach is used to form borderless contacts, then borderless contacts can be formed with less real estate, but the top portion of spacers is compromised during the RMG polishing step
Solution Approach 1:
The patent applies preliminary action by forming the gate conductor and spacers before the RMG polishing step. Specifically, the gate conductor is formed on the channel region, then spacers are formed on the gate conductor, and only then is the polishing step performed to remove the dummy gate. This sequence ensures that the spacers are already in place and protected during polishing, preventing the compromise that occurs when spacers are formed after polishing in conventional approaches.
Solution Approach 2:
The patent segments the gate structure into multiple components: a gate conductor portion formed on the channel region, spacers formed on the gate conductor, and a dielectric layer surrounding these structures. This segmentation allows each component to be formed and protected independently, enabling the spacers to be preserved during the polishing process while still achieving the borderless contact configuration with reduced real estate requirements.
2Reliability
If work function metal and metal gate are recessed to avoid contact with borderless contacts, then shorting is avoided, but the process complexity increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the gate conductor/spacers and the borderless contacts. This dielectric layer provides electrical insulation, preventing shorting between the work function metal/metal gate and the borderless contacts. By using this intermediary dielectric structure, the patent avoids the need for complex recessing operations while still achieving reliable electrical isolation, thus reducing process complexity compared to approaches requiring multiple recessing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the successful integration of borderless contacts in the GL-RMG process, maintaining the integrity of the transistor structure and reducing real estate requirements, while ensuring proper electrical insulation and avoiding shorting issues.
Implementation Method 1
removing the spacers includes applying a hot phosphorus solution to etch the spacers, the hot phosphorus solution causing little or no etching effect to the gate conductor
Implementation Method 2
etching the second portion of the work-function layer includes applying a directional etching process in the etching, wherein the directional etching process lowers a height of the work-function layer that is next to the sidewalls of the opening and lowers a height of the gate conductor
Implementation Method 3
subsequent dielectric material deposition to insulate the gate conductor
Data Source
AI summary
Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.