Boron-Doped Carbon Capping Layer for PMOS Channel Strain
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Solution Overview
Problem
Current methods for generating compressive strain in PMOS transistors, such as using compressive nitrides and SiGe, fail to achieve high enough stress levels and often require annealing that exceeds the thermal budget of transistor fabrication, limiting their effectiveness in enhancing hole mobility and current flow.
Innovation Solution
A highly compressive boron doped carbon capping layer is applied over the source and drain regions of PMOS transistors using a PECVD process, achieving compressive stresses exceeding 3.5 GPa without degrading the salicide layer or exceeding the thermal budget, thereby increasing channel strain and improving hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compressive nitrides are used to improve PMOS device performance, then hole mobility is enhanced, but annealing at elevated temperatures is required which significantly cuts into thermal budgets
Solution Approach 1:
The patent changes the material parameter from conventional compressive nitrides to boron-doped diamond-like carbon (DLC) film, which achieves comparable or superior compressive stress (3.0-3.5 GPa vs. up to 3.0 GPa) without requiring high-temperature annealing. The boron doping concentration (10^19 to 10^21 atoms/cm³) and film thickness (5-20 nm) are optimized to achieve the desired stress while maintaining compatibility with low-temperature fabrication processes.
Solution Approach 2:
The patent uses a composite structure consisting of boron-doped diamond-like carbon film combined with salicide layers on source/drain regions. This composite approach creates a synergistic effect where the DLC layer provides compressive stress and the salicide layers provide additional stress enhancement, achieving total compressive stress exceeding 3.0 GPa without high-temperature processing.
2Reliability
If SiGe is used to strain the channel region, then compressive stress is created increasing current flow, but the maximum permissible stack height is limited to 50 nm due to asymmetric strain buildup
Solution Approach 1:
The patent changes the material system from SiGe to boron-doped DLC, which provides comparable compressive stress (3.0-3.5 GPa vs. approximately 1 GPa for SiGe) without the asymmetric strain buildup problem. This allows for greater design flexibility in stack height and device architecture while maintaining effective channel strain.
3Reliability
If higher compressive stresses greater than 3.0 GPa are desired for PMOS transistors, then hole mobility can be further improved, but existing technologies cannot achieve these stress levels
Solution Approach 1:
The patent achieves compressive stress exceeding 3.0 GPa (specifically 3.0-3.5 GPa) by optimizing the boron doping concentration in the diamond-like carbon film to 10^19 to 10^21 atoms/cm³. This parameter optimization, combined with controlled film thickness (5-20 nm) and deposition conditions, enables the achievement of high compressive stress that exceeds conventional nitride-based approaches while remaining manufacturable.
Solution Approach 2:
The patent replaces the conventional mechanical strain induction method (SiGe epitaxial growth requiring precise lattice matching and limited thickness) with a stress-induced strain method using boron-doped DLC film. This substitution allows for higher achievable stress levels and greater design flexibility without the constraints of asymmetric strain buildup.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The boron doped carbon capping layer induces high compressive strain in the PMOS channel, significantly increasing saturation drive current and improving transistor performance beyond what is achievable with existing technologies, while preserving the material quality and thermal budget of the fabrication process.
Implementation Method 1
A highly compressive boron doped carbon capping layer is applied over the source and drain regions of PMOS transistors using a PECVD process
Implementation Method 2
a highly compressive boron doped carbon capping layer is provided on at least the source and drain regions to induce compressive strain in the PMOS channel region
Data Source
AI summary
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.