Boron Nitride Interconnect Structure for Low-k Dielectric Integrity

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Solution Overview

Problem

Existing semiconductor integrated circuit (IC) manufacturing processes face challenges in optimizing interconnection structures between layers of wires and associated dielectrics, which affect device performance.

Innovation Solution

The method involves a dual damascene process for fabricating interconnection structures, including the deposition of dielectric layers, metal vias, and trenches, with the use of etch stop layers and hard mask layers to achieve precise patterning and metal protection films to manage thermal conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional interconnection structures are used, then manufacturing is simpler, but device performance is insufficient

Engineering Contradiction:
Improvedevice performanceVSAvoidinterconnection structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interconnection structure is segmented into multiple functional layers: a first dielectric layer with through-holes, a second dielectric layer with recesses, and an etch stop layer. Each layer serves specific functions for signal transmission, insulation, and structural support, allowing complex performance requirements to be divided into manageable segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The structure uses composite material configuration with different dielectric layers (first dielectric layer, second dielectric layer) and conductive materials (conductive material in through-holes and recesses) combined with an etch stop layer. This composite approach enables simultaneous optimization of electrical performance, mechanical strength, and manufacturing controllability.

Inventive Principle:
Principle #40Composite materials

2Productivity

If dielectric layers are damaged during manufacturing, then manufacturing speed is faster, but dielectric constant increases and performance degrades

Engineering Contradiction:
Improvemanufacturing speedVSAvoiddielectric layer integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch stop layer is deposited in advance between the first and second dielectric layers before subsequent etching and filling operations. This preliminary protective action prevents damage to the dielectric layers during manufacturing processes, maintaining their integrity and low dielectric constants while enabling efficient production.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer acts as an intermediary protective layer between the first and second dielectric layers. It shields the dielectric layers from damage during etching and filling operations, allowing manufacturing to proceed at high speed without compromising dielectric layer integrity or increasing dielectric constants.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Temperature

If metal protection films are added to manage thermal conductivity, then thermal management improves, but device complexity increases

Engineering Contradiction:
Improvethermal conductivity managementVSAvoidstructure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The etch stop layer serves multiple functions simultaneously: it acts as a protective barrier during manufacturing, provides thermal management by controlling thermal conductivity between metal interconnections and dielectric layers, and maintains structural integrity. This multi-functionality reduces the need for separate dedicated thermal management layers, thereby limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250132247A1Interconnection structure
Publication Date: 2025.04.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250132247A1 patent drawing
  • US20250132247A1 patent drawing
  • US20250132247A1 patent drawing

AI summary

An interconnection structure is provided to include a substrate, a first metal trench, a boron nitride dielectric, a second metal trench, and a metal via. The substrate is formed with a first metal trench. The boron nitride dielectric is disposed over the substrate. The second metal trench is formed in the boron nitride dielectric. The metal via is disposed to interconnect the first metal trench and the second metal trench.