Boron Nitride Spacer Reduces Parasitic Capacitance in Semiconductor Memory

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Solution Overview

Problem

Silicon nitride layers used in semiconductor fabrication have a high dielectric constant, leading to increased parasitic capacitance and propagation delay as devices are scaled down, while boron nitride layers offer lower dielectric constants but are prone to hydrolysis, easy etching, and poor oxidation resistance.

Innovation Solution

The use of nitride layers containing boron and/or carbon, such as SiBN, SiBCN, SiCN, and BCN, as inter-layer dielectrics and spacers in semiconductor memory devices, deposited by atomic layer deposition (ALD) to reduce parasitic capacitance and enhance properties like oxidation resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If silicon nitride layers are used as insulating material, then excellent etching selectivity and abrasion resistance are achieved, but parasitic capacitance increases due to high dielectric constant

Engineering Contradiction:
Improveetching selectivityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric constant parameter by transitioning from silicon nitride (k≈7) to boron nitride (k≈2.2-5), thereby reducing parasitic capacitance while maintaining adequate etching selectivity for the specific application

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If boron nitride layers are deposited by ALD method, then low dielectric constant and conformal coverage are achieved, but oxidation resistance and hydrolytic stability deteriorate

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidoxidation resistance
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent employs composite material structures where boron nitride layers are combined with other materials or treated with protective coatings to achieve both low dielectric constant and improved oxidation resistance, creating a multi-functional insulating system

Inventive Principle:
Principle #40Composite materials

3Productivity

If device size is scaled down, then integration density increases, but parasitic capacitance effect becomes more significant due to high dielectric constant materials

Engineering Contradiction:
Improveintegration densityVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric material parameter to boron nitride with lower dielectric constant, which directly reduces parasitic capacitance effects and enables continued scaling while maintaining signal integrity and reducing propagation delay

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The nitride layers with boron and/or carbon effectively reduce parasitic capacitance, improve oxidation resistance, and maintain low dielectric constants, thereby enhancing the performance and reliability of semiconductor memory devices.

Implementation Method 1

BN layers are deposited at a low temperature of about 200° C. to 550° C. by an atomic layer deposition (ALD) method

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Data Source

PatentUS7763542B2Semiconductor memory device and method of fabricating the same
Publication Date: 2010.07.27 SAMSUNG ELECTRONICS CO LTD
  • US7763542B2 patent drawing
  • US7763542B2 patent drawing
  • US7763542B2 patent drawing

AI summary

A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.