Boron Seed Layer Reduces Buffer Thickness for CMOS
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Solution Overview
Problem
The integration of group III-V compound semiconductors on silicon substrates is limited by lattice constant and thermal expansion coefficient differences, leading to defects such as dislocation and cracking, and existing methods for growing high-quality germanium crystals are costly and time-consuming.
Innovation Solution
A substrate structure with a seed layer of boron or phosphorus and a buffer layer of germanium or SiGe is used to reduce the thickness of the buffer layer, improving crystallinity and reducing defects, while allowing for the growth of n-type and p-type transistors on a single silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If group III-V compound semiconductors are grown on Si substrates, then manufacturing cost is reduced and large-area production is enabled, but lattice constant difference and thermal expansion coefficient difference cause dislocation and cracking defects
Solution Approach 1:
A buffer layer comprising SiGe or Ge is introduced as an intermediary between the Si substrate and the group III-V compound semiconductor layer. This buffer layer gradually transitions the lattice constant from Si to the group III-V material, reducing dislocation defects caused by the lattice mismatch. The buffer layer also accommodates thermal expansion differences, preventing cracking while enabling cost-effective large-area Si substrate usage.
Solution Approach 2:
The lattice constant parameter is gradually changed through the buffer layer composition gradient. By controlling the Ge content in the SiGe buffer layer, the lattice constant transitions smoothly from the Si substrate value to the group III-V material value, minimizing dislocation density. This parameter transformation enables reliable heteroepitaxial growth on Si substrates.
2Reliability
If buffer layer thickness is increased to reduce defects, then crystal quality improves, but manufacturing time and cost increase
Solution Approach 1:
The Ge content parameter in the SiGe buffer layer is optimized to achieve the desired crystal quality with minimal thickness. By precisely controlling the composition gradient and Ge concentration, high-quality group III-V layers can be grown on thinner buffer layers, reducing manufacturing time while maintaining low defect density.
Solution Approach 2:
A standardized buffer layer structure with optimized composition and thickness is established through research and development. This standardized buffer layer design can be replicated across different production batches, ensuring consistent crystal quality without requiring excessive thickness, thereby reducing overall manufacturing time while maintaining reliability.
3Speed
If group III-V compound semiconductors are used for high-speed channels, then electron mobility increases significantly, but substrate selection is limited due to cost and availability constraints
Solution Approach 1:
The SiGe/Ge buffer layer acts as a mediator that enables the integration of high-performance group III-V compound semiconductors on abundant and cost-effective Si substrates. This intermediary structure preserves the high electron mobility benefits of group III-V materials while eliminating the substrate selection limitations, allowing versatile device fabrication on standard Si wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the thickness of the buffer layer, lowering manufacturing costs and time while maintaining high performance characteristics, thereby enhancing the quality and reducing defect density of the semiconductor layers.
Implementation Method 1
at least one seed layer provided on the substrate and formed of a material including boron (B) or phosphorus (P)
Data Source
AI summary
A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.