Bottle-Shaped Through Silicon Via for Heterogeneous Integration
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to deficiencies and performance limitations, particularly in connecting semiconductor dies with different design rules or critical dimensions.
Innovation Solution
A semiconductor device structure featuring a through silicon via with a bottle-shaped profile, allowing electrical connection between semiconductor dies with different design rules, utilizing a conductive layer, barrier layer, and lining layer, and a method for forming this structure that includes forming mask layers, etching, and depositing protective layers to create an enlarged opening for the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional through-silicon via structures are used, then manufacturing process is simpler, but connection between semiconductor dies with different design rules is limited
Solution Approach 1:
The patent applies asymmetry by creating a bottle-shaped through-silicon via with different cross-sectional areas at the top and bottom. The via has a larger bottom surface area than top surface area, allowing it to connect conductive pads of different sizes on upper and lower semiconductor dies. This asymmetric geometry enables compatibility between dies with different design rules and critical dimensions, directly resolving the contradiction between adaptability and structural complexity.
2Productivity
If semiconductor device integration is increased, then functionality and density are improved, but manufacturing complexity increases
Solution Approach 1:
The bottle-shaped via structure serves multiple functions: it provides electrical connection between dies, accommodates different pad sizes, enables bonding alignment tolerance, and supports various die size combinations. This multi-functional design allows a single via structure to handle diverse integration scenarios, increasing functional density without proportionally increasing manufacturing complexity.
3Reliability
If through silicon via interface area is increased, then electrical connection reliability is improved, but via structure complexity increases
Solution Approach 1:
The patent applies local quality by concentrating the enlarged cross-sectional area specifically at the bottom surface of the through-silicon via where it interfaces with the lower semiconductor die. This localized enlargement provides enhanced electrical connection and mechanical bonding area for reliability, while the upper portion maintains a smaller, simpler geometry. The selective application of complexity only where needed resolves the contradiction between reliability and overall structure complexity.
Data Source
AI summary
A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.